An offset voltage adjustment technique, which can be used to reduce the offset voltage of the buffer amplifier in the liquid-crystal display signal driver, is proposed. This adjustment, which is finished before driving the display panel, does not need to be adjusted for every row scanning cycle and does not increase the settling time. An experimental prototype output buffer implemented in a 0.3...

A simple analytical model has been developed to optimize biasing conditions for obtaining maximum linearity among lattice-matched, pseudomorphic and metamorphic HEMT types as well as enhancement and depletion HEMT modes. A nonlinear current-voltage model has been simulated based on extracted data to study and select the most appropriate type and mode of HEMT in terms of a given gate-source bias...

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active ...

This paper presents a fully integrated on-chip switched-capacitor (SC) DC–DC converter that supports a programmable regulated power supply ranging from 2.6 to 3.2 V out of a 5 V input supply. The proposed 4-to-3 step-down topology utilizes two conventional 2-to-1 step-down topologies; each of them (2-to-1_up and 2-to-1_dw) has a different flying capacitance to maximize the load current driving ...

This paper presents a new method to find the optimum switching angles in voltage source multilevel converters in order to minimize specific higher order harmonics and decrease the total harmonic distortion (THD) of their output voltage waveform. The output voltage waveform of inverter can either be in the form of staircase or PWM. In order to increase the degrees of freedom and elimination of m...

Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization is the key to low-power design. Threshold voltage scaling enables aggressive supply scaling but increases leakage power. Technology and circuit trends to control idle leakage power are presented including MTCMOS, variable VT bulk-CMOS, and variable VT Sol . Power can also be reduced by adaptiv...

At the time of power swing the measured impedance lies inside the relay operating region. There is undesired tripping of Distance relay during power swing without having any fault. So relay must be blocked & must trip after a fault occur during power swing. This paper presents new technique to detect fault during power swing. In the proposed technique process starts by simulating the double tra...

A phase-locked loop (PLL) and delay-locked loop (DLL) design with adaptively adjusting bandwidth enables optimal performance over a wide frequency range and across process, voltage, and temperature variations. A design methodology of such adaptive-bandwidth PLLs and DLLs is described. To assess the impact of each circuit parameter directly, we derive a discrete-time, open-loop dynamic model of ...