In a previous work we proposed a phase-lock structure called the time-delay digital tanlock loop (TDTL). This digital phase-locked loop (DPLL) performs nonuniform sampling and utilizes a constant time-delay unit instead of the constant 90-degrees phase-shifter used in conventional tanlock structures. The TDTL reduces the complexity of implementation and avoids many of the practical problems ass...

The paper presents “A CMOS Delay Lock Loop with Dual Control”. Positron emission tomography (PET) with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. Resolution is the biggest problem in PET. To achieve such resolution, time interpolations and multiphase sampling techniques are the mostly used methods. A preci...

This paper focuses on low cost production testing of the far-out phase noise of PLL ICs using the delay line discriminator method. It describes two different delay line discriminator (DLD) implementations for phase noise measurements at large frequency offsets from the carrier. The calibration method using an FM calibration signal is described in detail, both mathematically and graphically. The...

In this work classical and modern control theory methods are applied for rigorous mathematical analysis and design of different computer architecture circuits such as clock generators, synchronization systems and others. The present work is devoted to the questions of analysis and synthesis of feedback systems, in which there are controllable delay lines. In the work it is mathematically strict...

A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40 ) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fastlocking coarse acquisition is achieved in fo...