Although CMOS Time-of-Flight Range Image Sensors have been recently realized, the fabrication process is modified by inserting an extra mask layer to allow efficient TOF dependent charge transfer. This work focuses on the selection procedure of amplifiers to be used in the design of the TOF pixel using the standard CMOS process. From our analysis, it is found that the Cascode amplifier is the b...

Low Noise Amplifier, CMOS, Noise Canceling, Technique. This paper presents a 0.8V, 3.6GHz narrow band CMOS low noise amplifier (LNA). A current-reused technique is employed to increase the gain of LNA. Also, in order to achieve low noise figure, a noise canceling technique is used in the output stage. The high gain LNA was designed and simulated in 0.13 μm CMOS process. A gain of 27 dB at 3.6GH...

For realizing a single chip microwave front-end, we studied the new design theory of impedance matching circuits for a Si-CMOS low noise amplifier (LNA) or power amplifier (PA), which are composed of coplanar waveguide (CPW) meanderline resonators and impedance inverters. We also present the simulated performances of CMOS-LNA or PA connected with input and output matching circuits. Finally, we ...

This paper reports the design of a highly-linear CMOS amplifier for Variable Gain Amplifier (VGA) applications. A better than –60dB 3rd harmonic distortion at differential output level of 1V peak-to-peak is obtained by utilizing a linearization scheme that does not rely on the active devices. The amplifier maintains 3dB bandwidth over 300MHz. A noise figure at 8.6dB is obtained with source impe...

This paper presents the design of a CMOS RF Power Detector (PD) using 0.18 μm standard CMOS technology. The PD is an improved unbalanced source coupled pair incorporating an output differential amplifier and sink current steering. It realizes an input detectable power range of −30 to −20 dBm over 0.1–1 GHz. Also it shows a maximum data rate of 30 Mbps with 2 pF output loading under OOK modulati...

We have proposed a 2 GHz CMOS Differential Low Noise Amplifier (LNA) for wireless receiver system. The LNA is fabricated with the 0.18 μm standard CMOS process. Cadence design tool Spectre_RF is used to design and simulation based on resistors, inductors, capacitors and transistors. Power constrained methodology is used for the design of Differential Low Noise Amplifier. Consuming 9mA current a...

The design of A 2.4-GHz CMOS Class E cascode power amplifier (PA) for GSM applications in TSMC 0.18-μm CMOS technology present in this paper. Proposed Class E cascode PA topology is a single-stage topology in order to minimize the device stress problem. A parallel capacitor is connected across the transistors for efficiency enrichment also for dominating the effect of parasitic capacitances at ...

A single-stage 24 GHz triple stacked power amplifier using 0.13 μm CMOS process is demonstrated. To Compare with parallel current combining method, series voltage combining method using a stacked amplifier architecture can realize a large output voltage swing from the top transistor without exceeding the transistor breakdown voltage limitations. However, at high frequencies, parasitic capacitan...

Bluetooth Low Energy (BLE) is an advanced technology that has been designed as complementary technology to classic Bluetooth and also it is the lowest possible power wireless technology that can be designed and built. This paper provides an overview of bluetooth low energy technology and utilization of CMOS Low Noise Amplifier (LNA) for BLE applications. The aim of this paper is review and comp...