A shared well 4x4 SPAD array test structure with 3m pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.

A 10Ms/s 11-b algorithmic ADC with an active area of 0.19mm is presented. Using an improved clocking scheme, this design overcomes the speed limit of algorithmic ADCs. The proposed ADC employs amplifier sharing, DC offset cancellation, and input memory effect suppression to reduce area and power, and achieve high linearity. The ADC implemented in a 0.13μm thick gate-oxide CMOS process achieves ...

The trend in ADCs and DACs is toward higher speeds and higher resolutions at reduced power levels. Modern data converters generally operate on ±5V (dual supply) or +5V (single supply). In fact, many new converters operate on a single +3V supply. This trend has created a number of design and applications problems which were much less important in earlier data converters, where ±15V supplies and ...