This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16x16-b SAM and one 64x16-b SAM (consisting of four 16x16-b banks) has been designed, fabricated, and evaluated using a 0.25-μm CMOS process. With a clock frequency o...

We analyze a simple sequential algorithm (SA) for allocating indivisible items that are strictly ranked by n ≥ 2 players. It yields at least one Pareto-optimal allocation which, when n = 2, is envy-free unless no envy-free allocation exists. However, an SA allocation may not be maximin or Borda maximin—maximize the minimum rank, or the Borda score, of the items received by a player. Although SA...

We present a time-optimal implementation for bulk execution of an oblivious sequential algorithm. Our second contribution is to develop a tool, named C2CU, which automatically generates a CUDA C program for a bulk execution of an oblivious sequential algorithm. C2CU: A CUDA C Program Generator for Bulk Execution

This paper is concerned with the problem of reMizing a sequential machine M by a sequential circuit with a single feedback loop carrying a binary signal. To find such a realization, one must find a binary total-state partit ion, which can be used for feedback, for the flow table T of M or for some expanded version of T. A method is presented for testing whether a given flow table possesses a fe...