This paper presents a method for analyzing the Bit Error Rate of recovered data for PLL-based data recovery systems (DRS) as the PLL comes into lock. This method is based on the analyses of the transient response of the Phase-Locked Loop (PLL) and the associated jitter models. It provides a means to predict the acquisition time needed for a data recovery system to reach a given BER. Practical c...

We propose a novel all-optical structure of phase lock loop for locking two semiconductor lasers with a stable microwave offset for use in phased-array antenna systems.

We propose and demonstrate a 1.45GHz bandwidth optical phase-lock loop receiver for linear optical phase demodulation. Using the receiver in a link application, a spurious free dynamic range of 125 dBHz is measured at 300MHz. ©2007 Optical Society of America OCIS codes: (250.3140) Integrated optoelectronic circuits, (060.1660) , Coherent communications (060.5060), Phase modulation, (060.2360) F...

—For positioning with Global Navigation Satellite System (GNSS) in urban canyon area, besides the weak signal power, the satellite signal may also be frequently sheltered and no power can be received. It is a great challenge for the GNSS receiver to keep positioning continuously. If the tracking loop in GNSS receivers can recover locking the signal soon after the signal appears again, it will ...

Modernized GPS and Galileo will be available to civil users at the end of this decade. Their signal structure design will bring tremendous improvement for any user compared to current GPS. One important advance, which is the focus of this paper, is the availability of data and pilot (or data-less) channels wrapped in a Quadrature Phase Shift Keying (QPSK) modulation (or similar). The presence o...

This paper presents a Low power phase frequency detector with charge pump for low power phase lock loop. The phase frequency detector with dead zone compensation has been proposed. The paper contains the detailed circuit diagram of PFD and charge pump with 1.8v power supply and 500MHz input frequency. The design has been realized using 0.18um CMOS technology. Keywords— Low Power, PLL, PFD, CP

The phase-locked amplifier with output stability can filter out the noise effectively and the weak signal will be extracted from the noise and be amplified. The signal processing is relatively simple, so it is an effective way to detect the weak signal. It uses the phase sensitive detector (Phase Sensitive Detection, PSD) technique to identify the test signal, which has same frequency with the ...

This report presents two approaches for driving two-photon transitions between hyperfine states in the Rb ground state. These hyperfine states are intended for use as qubit states in quantum information processing with neutral atoms. The first approach uses microwave and radio frequency fields, and experiments on microwave singleand two-photon transitions showing the magnetically dependent Zeem...