The NIOS II soft core processor from Altera allows for the easy interfacing of new peripheral blocks to existing software. Using the Kakadu software implementation of JPEG2000, we have added dedicated hardware block encoders to produce an accelerated implementation. Simulation demonstrates that our simple architecture can provide a speedup of 2.55 times, compared to a pure software implementati...

Introduction Reducing power consumption in embedded products that use FPGAs is increasingly important, particularly for battery-powered applications or to reduce heat or cost. You can use parallel algorithms to exploit the parallel architecture of FPGA devices to accomplish more work per clock cycle, allowing you to lower the clock frequency. High-level development tools such as SOPC Builder an...

Analyzing the inverse kinematics theory and its solution method for 5R series manipulator, introducing the establishment of link coordinate system and D_H parameters for 5R series manipulator, studying the algorithm of inverse kinematics solutions based on FPGA controller for 5R manipulator, the system constructs the SOPC system architecture that is based on the Nios II CPU, uses the C program ...

The paper presents an implementation of a custom extension of commercially available NIOS processor embedded into Altera reconfigurable hardware. Added true random number generator uses recently proposed principle based on reconfigurable on-chip analog PLLs that are embedded in all modern Altera devices. Proposed solution significantly improves security of System on a Programmable Chip (SOPC) e...

In this paper we talk about mixed architectures of a H.264/AVC video decoder. Here software part of decoder was implemented in NIOS II processor on a FPGA prototyping board (Stratix III). Software and hardware architectures was proposed to increase the decoder output performance. Based upon the time execution parameters, data dependency constraints, the decoder partitioning is applied. Here the...

In this paper, a design of modularized dual-joint servo controller on-chip for a space manipulator system is presented. All sensor information collection within the joints are obtained with FPGA hardware logic elements, and the joint space trajectory planning and position control are realized by Nios II soft-core processor, which is embedded in FPGA. Moreover, a dualredundant CAN bus Interface ...

This paper presents a configurable base architecture tailorable for different applications. It allows simple and rapid way to evaluate and prototype large Multi-Processor System-on-Chip architectures on multiple FPGAs with support to Globally Asynchronous Locally Synchronous scheme. It allows early hardware/software co-verification and optimization. The architecture abstracts the underlying har...