Various compact models have been of great interest and studied for deep-submicron metal-oxide-semiconductor field effect transistor (MOSFET) device simulation. The model parameters extraction intrinsically characterizes properties of designed and fabricated devices. It leads to a multidimensional optimization problem to be solved and extracted efficiently for the applications to very large scal...

A simple, general, yet realistic MOSFET model, namely the nth power law MOSFET model, is introduced. The model can express I -V characteristics of short-channel MOSFET's at least down to 0.25-pm channel length and resistance inserted MOSFET's. The model evaluation time is about 1 / 3 of the evaluation time of the SPICE3 MOS LEVEL3 model. The model parameter extraction is done by solving single ...

Kufluoglu, Haldun Ph.D., Purdue University, December, 2007. MOSFET Degradation due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) and Its Implications for Reliability-aware VLSI Design . Major Professor: Muhammad A. Alam. The scaling trends in CMOS technology and operating conditions give rise to serious degradation mechanisms such as Negative Bias Temperature I...

A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. T...

This paper presents a new circuit arrangement for a current-mode Wheatstone bridge that is suitable for low-voltage integrated circuits implementation. Compared to the other proposed circuits, this circuit features severe reduction of the elements number, low supply voltage (1V) and low power consumption (<350uW). In addition, the circuit has favorable nonlinearity error (<0.35%), operate with ...

A SPICE (simulation program with integrated circuit emphasis) model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs and was implemented into a conventional circuit simulator. In the proposed model, the SET current calculated using an analytic model is combined with the parasitic MOSFET (metal-oxide semiconductor field effect transistor) ...

Device and circuit performance such as drain current and delay time varies stochastically due to uncontrollable factors in the fabrication processes. In this paper, a new method that represents the variation of the performance as worst case parameters in a MOSFET model is proposed. The variation of the performance can be expressed as a linear combination of several process-related parameters of...

Continued scaling of CMOS technology affects both, the parameters and the characteristics of MOSFET and the integrated circuit built on them and introduces some new problems in analog design. The reduction of the gate length and the gate oxide thickness led to improvements in terms of chip area, speed and power consumption. At the same time, nonlinear output conductance, reduced voltage gain an...

Circuit design of 2-input reconfigurable dynamic logic based on double gate MOSFETs with the whole set of 16 functions has been newly described. 16 function 12T DRDLC with two states (+V, 0) of control gate voltages and 14T DRDLC with two states (0, -V) of control gate voltages have been newly proposed. From these two states control gate case, 12T DRDLC with three states (+V, 0, -V) of control ...