In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...

In this article we characterize the effect of transmitter clock jitter upon receiver symbol synchronization performance. Using a sinusoidal model for the timing jitter, we evaluate the bit error rate (BER) degradation and cycle slip probabilities of receivers via analysis as well as simulation for uncoded offset quadrature-phase-shift-keying (OQPSK). We evaluate performance for two different sy...

Controlled amount of jitter injection into high speed serial bit stream is required for SerDes jitter tolerance test. While jitter injection by Direct Time Synthesis can be a much more cost effective method than a combination of several instruments, it is not widely used yet. Considering its high potential in high volume production test cost reduction, we have studied the basics of the jitter i...

Multimedia applications have the potential to enhance work for teams of users collaborating across distances. Jitter hampers the e ectiveness of these multimedia applications. Jitter is the variation in the end-to-end delay of data sent from one user to another. Jitter can cause silent gaps in the playout of an audio stream such as in an audioconference, or a choppy appearance to a video stream...

We added simulated vertical viewpoint jitter and oscillation to radial optic flow displays designed to induce forward vection. Display jitter and oscillation were both found to increase vection strength during, and reduce motion aftereffects (MAE) following, exposure to the optic flow (compared to no-jitter controls). Display jitter, which induced the strongest vection of all the conditions tes...

Jitter behavior has become increasingly critical design considerations for 12Gbps and 28Gbps transceiver devices featuring stringent specification compliance. In this paper, we present a comprehensive study of noise to jitter transfer mechanism, in which two dominant yet distinct jitter causes, power supply noise and signal crosstalk are investigated by phase noise method. The analysis reveals ...

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and shortchannel effects on the jitter and phase noise of ring oscillators is anal...

Phase noise and jitter are two related quantities associated with a noisy oscillator. Phase noise is a frequency-domain view of the noise spectrum around the oscillator signal, while jitter is a timedomain measure of the timing accuracy of the oscillator period. This paper discusses the relationship between phase noise and jitter in free-running oscillators. The reader is referred to three othe...