| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using di erent delay models such as unit delay, fanout delay, and random delay in power estimation of ...

This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit The transient energy is minimized when every gate has no more than one output transition per clock cycle This condition is achieved for a gate when the gate delay equals or exceeds the maxi mum di erence between path delays at gate inputs In practice path...

The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This ...

A dynamic delay model, which includes the nonlinear loading effect, the effects of the input transition time and the multiple-input triggering, is proposed for the gate-level timing simulation. It is shown that the developed delay model gives near circuit-level accuracy with comparable speed to other common delay models.

in this paper, behavior of teleoperation systems with modeling error and delay time error in smith predictor is discussed. in teleoperation systems, modeling error is inevitable. this paper discusses stability of teleoperation systems with modeling error. first, error of delay time in teleoperation systems by using of internet as communication channel is considered and the performance of smith ...

Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, are easily invalidated by hazards. The invalidation of non-robust tests occurs primarily due to non-zero delays of off-path circuit elements. Thus, non-robust tests are of limited value when process variations cause gat...

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus it may cause functional failures in the circuit. Therefore accurate prediction of circuit aging i...

As technology scales down, timing verification of digital integrated circuits becomes an extremely difficult task due to the gate and wire variability. Therefore, statistical timing analysis (denoted by σTA) is becoming unavoidable. In this paper, two new approaches for doing statistical gate timing analysis for Gaussian and non-Gaussian sources of variation in block-based σTA are presented. To...

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation exper...

5.1 Introduction The increasing circuit operating frequencies and demands for low cost and high quality require that the temporal correctness of the circuit can be guaranteed. For high performance circuits with aggressive timing requirements, small process variations can lead to failures at the design clock rate. These defects can stay un-detected after at-speed or stuck-at-fault testing. Delay...