floorplanning is an important step in physical design of vlsi circuits. it is used to plan the positions of a set of circuit modules on a chip in order to optimize the circuit performance. however, modern floorplanning takes better care of providing extra options to place dedicated modules in the hierarchical designs to align circuit blocks one by one within certain bounding box for helping seq...

The ability to improve the yield of integrated circuits through layout modification has been recognized, and several techniques for yield enhanced routing and compaction have been developed. Still, yield issues are rarely a factor in the choice of the floorplan mainly due to the tendency to focus on the more important timing and area objectives. Consequently, floorplanning tools have been devel...

ÐThe traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that, for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in add...

Temperature has a negative impact on metal resistance and thus wire delay. In state-of-the-art VLSI circuits, large thermal gradients usually exist due to the uneven distribution of heat sources. The difference in wire temperature can lead to performance mismatch because wires of the same length can have different delay. Traditional floorplanning algorithms use wirelength to estimate wire perfo...

As 3D chip multi-processors (3D-CMPs) become the main trend in processor development, various thermal management strategies have been recently proposed to optimize system performance while controlling the temperature of the system to stay below a threshold. These thermal-aware policies require the envision of high-level models that capture the complex thermal behavior of (nano)structures that b...

Next generation deep submicron processor design will need to take into consideration many performance limiting factors. Flip flops are inserted in order to prevent global wire delay from becoming nonlinear, enabling deeper pipelines and higher clock frequency. The move to 3D ICs will also likely be used to further shorten wirelength. This will cause thermal issues to become a major bottleneck t...

This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based flo...