Article history: Received 15 April 2006 Received in revised form 7 August 2008 Accepted 16 August 2008

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

In this paper, we present a novel approach to comprehensively verify timing sensitive blocks, specifically Delay Lines and Delay Locked Loops by modelling transient behavior into the RTL. This paper focuses on reduction of simulation time and increase in design turnaround time. Information gathered from a small set of spice simulations is modelled into a Verilog based environment, which gives s...

The rapid growth in telecommunication traffic demands a higher-speed asynchronous transfer mode (ATM) switching system. At present, the upper limit of the system clock rate is determined by the maximum clock rate of conventional semiconductor memory devices, such as the register files used in ATM cell buffer storage. This is because the maximum clock rate of these register files is restricted b...

Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum...