Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect...

technology with through-silicon vias and low-volume leadfree interconnections K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidt...

Lamb waves are dispersive in a plate and elastic properties of anisotropic materials are dependent on the crystal orientation. It is expected that the wave propagation on a thin anisotropic plate is complex due to dispersion of Lamb waves which will be dependent on the propagation direction. Therefore it is essential to understand elastic waves in an anisotropic plate. In the present work, a si...

Lateral carrier diffusion can lead to significant smearing in photoluminescence (PL) images of silicon wafers with high lifetime or localised recombination centres. A method to de-smear the PL image by applying the continuity equation in two dimensions has been proposed previously and demonstrated on a virtual wafer with simulated carrier diffusion and artificial random Gaussian noise. This wor...

Silicon-on-insulator (SOI) wafers are nowadays being prominently used for the manufacture of new generation semiconductor devices. In order to maximize the device yield, the device industry is seeking SOI wafers that meet very stringent wafer specifications such as very low wafer bow and warp. An SOI wafer can undergo severe process-induced stresses during its manufacture leading to significant...

When prepared on a silicon wafer and annealed above the glass transition

Heterojunction solar cells have potential for very high device voltages and currents, yet this relies on correct preparation of wafer surfaces prior to a-Si deposition. This paper investigates the preparation of wafer surfaces by NaOH texturing prior to amorphous silicon intrinsic layer deposition. It is found that with a CP etch or low temperature anneal after texturing, and with correct depos...

There is a constant desire to increase substrate size in order to improve cost effectiveness of semiconductor processes. As the wafer diameter has increased from 2” to 12”, the thickness has remained largely the same, resulting in a wafer form factor with inherently low stiffness. Gravity induced deformation becomes important when using traditional metrology tools and mounting strategies to cha...

A micropyramid structure was formed on the surface of a monocrystalline silicon wafer (100) using a wet chemical anisotropic etching technique. The main objective was to evaluate the performance of the etchant based on the silicon surface reflectance. Different isopropyl alcohol (IPA) volume concentrations (2, 4, 6, 8, and 10%) and different etching times (10, 20, 30, 40, and 50 min) were selec...

This study presents a novel system architecture to implement silicon-on-glass (SOG) MEMS devices on Si–glass compound substrate with embedded silicon vias. Thus, the 3D integration of MEMS devices can be accomplished by means of through-wafer silicon vias. The silicon vias connecting to the pads of devices are embedded inside the Pyrex glass. Parasitic capacitance for both vias and microstructu...