Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very...

Voltage scaling has been often used for reducing power dissipation of CMOS driven interconnects. An undesired effect observed due to voltage scaling is increase in propagation delay. Thus a trade off lies between power dissipation and propagation delay with voltage scaling. However, voltage scaling can result in overall reduction of power delay product (PDP). Therefore, their lies an optimized ...

Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...

A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) b...

scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. one of the most promising and possible nano-technologies is cnt (carbon nanotube) based transistors. cnfet have emerged as the more practicable and promising alternative device compared to the other nanotechnologies.  this technology has higher efficiency compared to t...

The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modu...

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is paramount requirement portable devices employing various processors. this work novel speed one-bit 10T full adder with complemented output was described. The constructed XOR gates which were built using two CMOS transistors. gate 2T multiplexer styl...

Design of a new sense amplifier-based flip-flop (SAFF) using GDI Technique and performance comparison of proposed SAFF with existing conventional SAFF with CMOS-NAND latch SAFF and SAFF with CMOS Symmetric latch is presented in this paper. It was found that the main drawback of existing SAFF’s is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output sta...

The paper proposes a novel design of two transistor (2T) XOR gate and its application to design an 8 bit x 8 bit multiplier. The design explores the essence of suitably biasing the MOS transistor and engineering the threshold voltage of the MOS transistor through appropriate biasing and device geometry. Using the 2T XOR gates, a full adder has been realised. Detailed simulations have been carri...

Power consumption and delay are two important considerations for VLSI systems. The objective of this project is to reduce the power and to reduce the delay which increases the speed. Adders are very important components in many applications such as microprocessor and digital signal processing (DSP) architectures. Full Adder is one of the core elements. It used in many of the complex arithmetic ...