In this paper, we propose a gate-level NBTI delay degradation model, where the stress voltage variability due to PMOS transistors’ stacking effect is considered for the first time. Experimental results show that our gate-level NBTI delay degradation model results in a tighten upper bound for circuit performance analysis. The traditional circuit degradation analysis leads to on average 59.3% ove...

We examine the problem of mapping a Boolean network using gates from a finite size cell library. The objective is to minimize the total gate area subject to constraints on signal arrival time at the primary outputs. Our approach consists of two steps: In the first step, we compute delay functions (which capture gate area – arrival time tradeoffs) at all nodes in the network, and in the second s...

Airport gate assignment is to appoint a gate for the arrival or leave flight and to ensure that the flight is on schedule. Assigning the airport gate with high efficiency is a key task among the airport ground busywork. As the core of airport operation, aircraft gate assignment is known as a kind of complicated combinatorial optimization problem. This paper proposed robust assignment model to m...

Levelized Compiled Code (LCC) multi-delay simulation is an idea whose time has come. Although it is not a new idea, when it was first proposed the hardware and software technology of the time was not capable of meeting the demands of such a simulation technique[1]. The basic technique is to predict the points in time when each gate can change value, and generate simulation code to compute the o...

A gate delay test generator for circuits with three-state elements and standard scan-design is presented. The pattern generator combines a well proven stuck-at test pattern generator and a gate delay fault simulator that is used to evaluate the quality of the generated gate delay tests. Experimental results show how the reduced controllability of primary inputs of embedded cores effects the del...

| The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using diierent delay models such as unit delay, fanout delay, and random delay in power estimation of ...