We present an optical frequency divider based on a 200 MHz repetition rate Er:fiber mode-locked laser that, when locked to a stable optical frequency reference, generates microwave signals with absolute phase noise that is equal to or better than cryogenic microwave oscillators. At 1 Hz offset from a 10 GHz carrier, the phase noise is below -100 dBc/Hz, limited by the optical reference. For off...

In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are re...

This paper presents the design and simulated performance of an ultra-low-power 4/5 frequency divider based on a CMOS ring oscillator. The divider operates over a 189% locking range (29MHz – 1GHz) for both division ratios, covering the MICS band and 433MHz and 915MHz ISM bands while consuming only 3.3 μW in MICS band. The wide locking range and low power consumption makes this very suitable for ...

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capaciti...

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the o...

This paper describes a multiple access technique suitable for indoor wireless ATM networks that exploits both frequency division and time division techniques for channel re-use (i.e. FDMA/TDMA). The novel feature of the proposed technique is that co-ordinated, prioritised TDMA is supported for clusters of Access Point’s (AP’s) using measurement based time slot assignments. This has the advantag...

In this paper, we present a broadband out-of-phase power divider with high power-handling capability. The proposed device consists of several sections of double-sided parallel-strip lines (DSPSLs), a mid-inserted conductor plane, and two external isolation resistors, which are directly grounded for heat sinking. A through ground via (TGV), connecting the top and bottom sides of DSPSLs, is emplo...

An ultra-wide locking range transformer-based injection-locked frequency divider (ILFD) is presented. By making use of a 4-order transformer-based resonator and an inductive gain peaking technique, the proposed ILFD can achieve high performance in terms of wide locking range and low power consumption. Fabricated in a standard 65nm CMOS process with a core area of 0.18mm, the ILFD measures a loc...