This thesis examines methods for generation of heterogeneous reconfigurable hardware based on formal optimisation methods. As reconfigurable hardware has evolved, an increasing number of different embedded component types have been made available on reconfigurable devices. Existing techniques for generating hardware and analysing the advantages of different embedded components are heuristic bas...

In recent years, neuromorphic computing systems based on memristive crossbar have provided a promising solution to enable acceleration of neural networks. Meanwhile, most of the neural networks used in realistic applications are often sparse. If such sparse neural network is directly implemented on a single memristive crossbar, it would result in inefficient hardware realizations. In this work,...

An important step in the automation of electronic design is the assignment of the physical components on the target semiconductor die. The major aim of floorplanning is to distribute the modules of a circuit onto a chip to optimize its area, wire length and timing. As the density of very large scale integrated (VLSI) circuits enhance, the need for faster floorplanning algorithms also grows. The...

An important step in the automation of electronic design is the assignment of the physical components on the target semiconductor die. The major aim of floorplanning is to distribute the modules of a circuit onto a chip to optimize its area, wire length and timing. As the density of very large scale integrated (VLSI) circuits enhance, the need for faster floorplanning algorithms also grows. The...

Confronted with the challenge of high performance for applications and the restriction of hardware resources for field-programmable gate arrays (FPGAs), partial dynamic reconfiguration (PDR) technology is anticipated to accelerate the reconfiguration process and alleviate the device shortage. In this paper, we propose an integrated optimization framework for task partitioning, scheduling and fl...

In this work we present a probabilistic approach to simultaneous floorplanning and resource binding for low power. Traditional approaches iteratively perform floorplanning and resource binding while using crude deterministic wire-length estimates like bounding box (since we do not have routing information for inter module interconnect). Nonavailability of accurate wire-length results in subopti...

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architect...

Floorplanning/placement allocates a set of modules into a chip so that no two modules overlap and some specified objective is optimized. To facilitate floorplanning/placement, we need to develop an efficient and effective representation to model the geometric relationship among modules. In this paper, we present a P-admissible representation, called corner sequence (CS), for nonslicing floorpla...

In this work, we study multiobjective thermal-aware floorplanning in the fixed-outline context. Our baseline implementation demonstrates a 14% average interconnect improvement over Parquet for ami49, and can additionally optimize peak on-chip temperature. To circumvent the expense of Compact Thermal Models, we develop a novel approach to power-density aware floorplanning, but rigorously evaluat...