In this paper, we propose a High Availability Open Shortest Path First (HA-OSPF) router which consists of two OSPF router modules, active and standby, to support a high availability network. First, we used the continuous-time Markov chain (CTMC) to analyze the steady-state availability of an HA-OSPF router with one active router and N standby routers (1 + N redundancy model). Then, with the fai...

Current router models [2, 3, 5, 6] assume that clock cycle time depends solely on router latency. However, in practice, routers are heavily pipelined, making cycle time largely independent of router latency. In this paper, we describe a router delay model that accurately accounts for pipelining based on technology-independent delay estimates derived through detailed gate-level analysis. Simulat...

With the rapid increasing of network traffic, whether the router can be scalable is becoming the issue that people concern. The cluster-based scalable router can increase the capability infinitely in theory with linearly cost. Without the concentrated switch fabric, the operations of routing and forwarding are different from the typical crossbar router. The incoming packets usually pass through...

Abstract One of the primary challenges in realizing large-scale quantum processors is realization qubit couplings that balance interaction strength, connectivity, and mode confinement. Moreover, it very desirable for device elements to be detachable, allowing components built, tested, replaced independently. In this work, we present a microwave state router, centered on parametrically driven, J...

OSPF, or Open Shortest Path First, is a commonly used interior gateway protocol. An integer weight is assigned to each arc and the entire network topology and arc weights are known to each router. Each router computes a graph of shortest weight paths from itself to every other router in the network. Traffic is routed on the shortest weight paths. All traffic leaving router s with destination ro...

A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on the substrate, the objective of the router is to complete the planar interconnection of pad-to-pin nets on one or more layers. This router consists of three phases: layer assignment, topological routing, and geometric...