There is a constant desire to increase substrate size in order to improve cost effectiveness of semiconductor processes. As the wafer diameter has increased from 2” to 12”, the thickness has remained largely the same, resulting in a wafer form factor with inherently low stiffness. Gravity induced deformation becomes important when using traditional metrology tools and mounting strategies to cha...

This paper focuses on production scheduling in a semiconductor wafer fab producing multiple product types that have different due dates and different process flows. In the wafer fab, wafer lots are processed on serial and batch processing workstations, each of which consists of parallel identical machines. Machines in serial processing workstations process wafer lots one by one, while those in ...

Occlusal wafers are commonly used to establish the intermediate and final position of the occlusion during orthognathic operations. Various problems have been experienced in the construction of these wafers. Acrylic wafers have poor compressive and tensile characteristics, take time to make, and are bulky. They can also distort while curing, increasing the risk of inaccurate localization of the...

This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer su...

INTRODUCTION Wafer Level Packages have emerged as the fastest growing semiconductor packaging technology. Rather than a single solution, wafer level packaging technologies are a set of different solutions including flip-chip wafer bumping, electroplated gold, solder bumps and recent copper pillar technologies. These chips can be

Northrop Grumman Space Technology has demonstrated the capability to manufacture intra-cavity interconnections (ICICs), which consistently yield greater than 99%. These ICICs are an integral part of MMICs packaged at the wafer level using wafer bonding techniques. Efficient test structures were designed to evaluate these interconnects, allowing fast on-wafer assessment of interconnect yield in ...

FlexLineTM is an innovative manufacturing approach that provides freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions not possible with a conventional manufacturing flow. This breakthrough approach delivers unprecedented flexibility in producing both fan-out wafer level packages (FOWLP) and fan-in wafer level chip scale packages (WL...

A wafer-level functionality testing and characterisation system for ISFETs (ionsensitive field-effect transistor) is realised by means of integration of a specifically designed capillary electrochemical micro-droplet cell into a commercial wafer prober-station. The developed system allows the identification and selection of “good” ISFETs at the earliest stage and to avoid expensive bonding, enc...