......As circuit feature sizes shrink, their capacitance and operating voltage become smaller, making it easier for a particle strike to influence circuit behavior. Technologies such as silicon on insulator (SOI) and FinFET significantly counteract this effect by decreasing the sensitive area in the transistor. However, the resulting single-event upset (SEU) rate is still nontrivial for common ...

This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kΩ L-resistor hardening scheme provides greate...

We have investigated the effects produced by exposing a Field Programmable Gate Array (FPGA) based on static RAM to an Ion Beam. Tested devices have been taken from FLEX10K family manufactured by Altera Corporation. These parts are commercial graded and not qualified for application in radioactive environments. A design based on mixed plain and Triple-Modular-Redundant (TMR) shift registers (SR...

SRAM-based reconfigurable programmable logic is widely used in commercial applications and occasionally used in space flight applications because of its susceptibility to singleevent upset (SEU). Upset detection and mitigation schemes have been tested on the Xilinx Virtex II X-2V1000 in heavy-ion and proton irradiation to control the accumulation of SEUs and to mitigate their effects on the int...

Carbon nano tube devices are considered as a better replacement for CMOS technology nowadays due to its decreased sizing and increased performance. Resistive open and bridging faults play vital role in the dynamic fault analysis. These faults are important since the number of interconnects have increased. In this study we discuss the effect of open and bridging defects along with the variation ...

Soft errors are intermittent malfunctions of hardware that are not reproducible. They may affect the data integrity and affect the system operation. These errors are growing reliability threat in VLSI system design. A soft error occurring in a memory cell or register is called a Single Event Upset (SEU). Designs mapped into Field Programmable Gate Arrays (FGPAs) are more vulnerable to soft erro...

This paper explores the feasibility of Tierra-based OBC that evolves programs through a bit inversion caused by Single-Event Upset. In particular, Tierra-based OBC is applied to the evolution of the PIC assembly programs. Additionally, this paper proposes a new method that can reliably recover the broken program to the correct one. Intensive experiments reveal that (1) Tierra-based OBC cannot o...

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which can be induced by radiation effects. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. In this work, we propose techniques for SEU mitigation and recovery of a soft-core processor using triple modular redundancy (TMR) and partial reconf...

The fast growing VLSI industry demands new techniques for configuring the FPGA. When it comes to defence and space application the configuration of the FPGA becomes more crucial. When it is required to configure the FPGA automatically, the need arises of more sophisticated and fast techniques for reconfiguration of FPGA. In the space application, the effect of radiation changes the bit patterns...