Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken deal with for field effect transistor further scale down as semiconductor technology enters into sub-10 nm node. From 3 node beyond, gate all around steps onto the history stage attributed its improved SCE suppressing ability thanks surrounding s...

This paper present the electron charge pumping technique using the various charge pumps circuits for interface trap density and edge leakage reduction that is major concern in GAA short channel nanowire structure. Latched and bootstrap charge pump circuit has been simulated and analyzed for GAA structure. The charge pumping technique requires body contact of FET which has been implemented for G...

A biocompatible and functional interface can improve the sensitivity of bioelectronics. Here, 3-aminopropyl trimethoxysilane (APTMS) and 3-mercaptopropyl trimethoxysilane (MPTMS) self-assembled monolayers (SAMs) were independently modified on the surface of silicon nanowire metal-oxide-semiconductor field effect transistors (NW-MOSFETs). Those SAMs-modified silicon NW-MOSFETs were used to discr...

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and ...

Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET because most of TFETs are assumed to use on SOI substrates. In this p...

--In today’s technological environment, there is a huge demand for devices with low power and low cost storage space. Memories with low power are driving the entire VLSI industry as most of the devices work on remote power supply. Demand of low power becomes the key of VLSI designs rather than high speed, particularly in embedded SRAM’s and caches. The tunneling field effect transistor uses the...

A novel gate-all-around (GAA) poly-Si nanowire (NW) floating gate (FG) memory device was fabricated and characterized. The enhanced electric field around the corners of the nanowire channels boosts the P/E process and thus the operation voltages are dramatically lowered. Furthermore, the non-localized trapping feature characteristic of the FG makes the injection or ejection of electrons easier ...

An efficient antireflection coating is critical for the improvement of silicon solar cell performance via increased light coupling. Here, we have grown well-aligned ZnO nanowhisker (NW) arrays on Czochralski silicon solar cells by a seeding-growth two-step process. It is found that the ZnO NWs have a great effect on the macroscopic antireflection effect and, therefore, improves the solar cell p...

Formation of a selective emitter in crystalline silicon solar cells improves photovoltaic conversion efficiency by decoupling emitter regions for light absorption (moderately doped) and metallization (degenerately doped). However, use of a selective emitter in silicon nanowire (Si NW) solar cells is technologically challenging because of difficulties in forming robust Ohmic contacts that interf...