The interconnect delay in the new generations of integrated circuits imposes a significant limitation on the performance of ICs. 3-Dimensional integration of integrated circuits had been proposed to improve the interconnect delay. In this research, the effect of 3-D integration on the delay and power of FPGA chips is analyzed. Different physical partitioning of FPGAs is proposed for 3-D integra...

It has been observed experimentally that the mapping of global to detailed routing in conventional FPGA routing architecture (2D array) yields unpredictable results. In [8,10,13], a different class of FPGA structures called Greedy Routing Architectures (GRAs), where a locally optimal switch box routing can be extended to an optimal entire chip routing, were investigated. It was shown that GRAs ...

Field-Programmable Gate Arrays (FPGAs) have recently emerged as an attractive means of implementing logic circuits as a customized VLSI chip. FPGAs have gained rapid commercial acceptance because their user-programmability offers instant manufacturing turnaround and low costs. However, FPGAs are still relatively new and require architectural research before the best designs can be discovered. O...

We study a new family of geometric graphs that interpolate between the Delaunay triangulation and the Gabriel graph. These graphs share many properties with βskeletons for β ∈ [0, 1] (such as sublinear spanning ratio) with the added benefit of planarity (and consequently linear size and local routability).

Abstract This paper presents a new stochastic model for two dimensional layouts of large size. Two problems are addressed: (i) Under the condition that the number of wires emanating from a block is Poisson distributed, determine the distribution of channel width, thus estimating the average channel width. (ii) Given T tracks for each channel, determine the success probability of routing an M×M ...

Deep sub micron e ects along with increas ing interconnect densities have increased the complexity of the routing problem Whereas previously we could fo cus on minimizing wirelength we must now consider a vari ety of objectives during routing For example an increased amount of timing restrictions means that we must minimize interconnect delay But interconnect delay is no longer simply related t...

Information does not generally behave like a flow in communication networks with multiple sources and sinks. However, it is often conceptually and practically useful to be able to associate separate data streams with each source-sink pair, with only routing and no coding performed at the network nodes. This raises the question of whether there is a nontrivial class of network topologies for whi...

A fundamental difference between ASICs and FPGAs is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, area is fixed and routing resources exist whether or not they are used. Modern FPGAs have the logic and routing resources to implement networks of multiprocessor systems, and system-level interconnection becomes a key element of the d...

An integrated standard-cell physical design algorithm (ISCPD) is presented. A spine net topology is adopted, enabling quick construction of the placement and routing of a standard-cell design with guaranteed routability. Experiments show that ISCPD is comparable to commercial placement and routing tools in terms of area and wire length but several times faster, making it very suitable for physi...