The technology scaling impact on FinFET-based Field-Programmable Gate Array (FPGA) components (Flip-Flops and Multiplexers) and cluster metrics is evaluated for technology nodes starting from 20 nm down to 7 nm. Power consumption, delay and energy (Power Delay Product, or PDP) trends are reported with FinFET technology scaling. Cluster metrics are then evaluated based on three benchmarking circ...

Background: At present scenario, the frequent and the most fundamental component in low power processor design is Arithmetic and Logic Unit (ALU). Further Power utilization due to clock gated ALU can be noteworthy in high performance systems. In general functionality of the ALU's is a mixture of arithmetic and logic operations which are realized by means of combinational circuits. In attendance...

In this chapter we have discussed the research work done on the basis of literature review and study. The research methodology and the techniques to modify the present designs in order to achieve better performance have been discussed with their merits and demerits. In this paper FS-SERF and HSSERF full adder topologies are presented. The analysis of Power, Delay, Power Delay Product (PDP) opti...

In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of sp...

High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e...

In any integrated circuit power consumption plays a paramount role and is considered as one of the top challenges in International technology roadmap for semiconductors. In this paper, a low power circuit designed to operate in subthreshold region is proposed. Voltage scaling technique is incorporated to reduce dynamic power consumption while static or leakage power is greatly reduced with forc...

Recently low power circuits have become a top priority in modern VLSI design. This paper presents post layout simulations of a new improved 2:1 multiplexer design. The proposed design demonstrates its superiority against existing 2:1 multiplexer design in terms of power–delay product (PDP), temperature sustainability, noise immunity and frequency. All the post-layout simulations have been perfo...

This paper presents high speed and low power full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first desig...

The aim of this paper is to design Carbon Nanotube Field Effect Transistor-based (CNTFET-based) combinational circuits with improved Power Delay Product (PDP). Ternary logic circuits have attracted substantial interest due to their capability of increasing information content per unit area. As a result, the geometry-dependent threshold voltage of CNTFETs is effectively used to design a ternary ...