quantum-dot cellular automaton (qca) is a novel nanotechnology with a very different computational method in compared with cmos, whereas placement of electrons in cells indicates digital information. this nanotechnology with specifications such as fast speed, high parallel processing, small area, low power consumption and higher switching frequency becomes a promising candidate for cmos technol...

Background and Objectives: Recently, photonic crystals have been considered as the basic structures for the realization of various optical devices for high speed optical communication. Methods: In this research, two dimensional photonic crystals are used for designing all optical logic gates. A photonic crystal structure with a triangular lattice is proposed for making NAND, XNOR, and OR optica...

The cost of delay is a serious and increasing problem in the airline industry. Air travel is increasing, and already domestic airports incur thousands of hours of delay daily, costing the industry $2 billion a year. One strategy for reducing total delay costs is to hold planes for a short time at the gate in order to reduce costly airborne congestion. In a network of airports involving hundreds...

In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins...

application of quantum-dot is a promising technology for implementing digital systems at nano-scale.  quantum-dot cellular automata (qca) is a system with low power consumption and a potentially high density and regularity. also, qca supports the new devices with nanotechnology architecture. this technique works based on electron interactions inside quantum-dots leading to emergence of quantum ...

We propose an exact clustering with retiming algorithm to minimize the clock period for sequential circuits. Without moving ip-ops (FF's) by retiming, conventional clustering algorithms can only handle combina-tional parts and therefore cannot achieve the best cycle time. Pan et al. 2] have proposed an optimal algorithm under the unit gate delay model. We propose a more powerful and faster algo...

Table 1: The TAG table for a two-input AND gate. cir-unit delay uit power estimation run time % speed ss tp err. ss tp up s349 265. Run-time under a unit delay model: ss : using symbolic simulation, tp : using transition probability. cir-fixed binary inertial delay uit power estimation run time % speed ss tp err. ss tp up s349 231.

Previous work has shown that maximum switching density at a given node is extremely sensitive to a slight change in the delay at that node. However, when estimating the peak power for the entire circuit, the powers estimated must not be as sensitive to a slight variation or inaccuracy in the assumed gate delays because computing the exact gate delays for every gate in the circuit during simulat...

Power is increasingly the primary design constraint for chip designers and one of the main techniques for addressing this concern is aggressive voltage scaling. Device variability increases with voltage scaling and significantly affects gate delays at low voltages. Although existing delay models for nearand sub-threshold circuits captures the effects of variability on gate delays, they do not c...

A unified and consistent representation of logic gates at logic and circuit levels is described based on the subcircuit expansion approach. A dynamic-delay model is proposed for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering on the delay. It is shown that the approach provides near circuit-level accu...