The GaSb surface was exposed to various HCl-based chemical treatments in order to prepare it for high-k dielectric integration. The chemical and structural analysis was performed by X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). The chemical analysis indicates the HCl effectively removes native oxide from GaSb surface and leaves it slightly antimony rich. The structur...

The dielectric properties of Au/Si3N4/n-Si (MIS) structures are studied using the admittance measurements (C–V and G/ω–V ) each as a function of temperature in a range from 80 K to 400 K for two frequencies (100 kHz and 1 MHz). Experimental results show that both the dielectric constant (ε ′) and the dielectric loss (ε ′′) increase with temperature increasing and decrease with frequency increas...

The scaling of silicon-based MOSFET technology beyond the 22 nm node is challenging. Further progress requires new channel materials such as Ge, III-V semiconductors, carbon nanotubes (CNTs) and graphene. Perfect top-gate dielectric stacks are needed in order to sustain their potential device performance for carbon nanoelectronics. Due to the inert nature of carbon surfaces of CNTs and graphene...

For the 45nm technology node, high-k+metal gate transistors have been introduced for the first time in a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled a 0.7x reduction in Tox while reducing gate leakage 1000x for the PMOS and 25x for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion...

Article history: Available online xxxx a b s t r a c t Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engin...

When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the int...

The dielectric and conduction behavior of SrTiO3 thin films deposited on a SrTiO3 single-crystal substrate is studied. Without dc bias, an obvious dielectric ‘‘defect mode’’ in the dielectric loss is observed in the temperature range of ;100–200 K; however, no noticeable corresponding dielectric constant peak is observed. By applying a high dc bias ~>40 kV/cm!, a dielectric constant peak with f...

The second polymorph, the β-crystal, of the nickel-bis-dithiolene compound [4'-CF3bzPy][Ni(mnt)2], where 4'-CF3bzPy = 1-(4'-trifluoromethylbenzyl)pyridinium and mnt(2-) = maleonitriledithiolate, was obtained. The variable-temperature single crystal structures, magnetic behavior in 1.8-300 K and dielectric nature in 123-373 K have been investigated for the β-crystal. This polymorph experiences t...

although in recent two decades, the concept of dielectric barrier discharges (dbds) have been developed in ozone production well, air pollution control, plasma screens and control of chemical, and biological and medical processes, employment of this concept for high voltage applications to improve insulation performance as an alternative to the pressurized gas-insulated systems (gis) utilizing ...