Abstract Virtual FPGAs (V-FPGAs) are used as vendor-independent virtualization layers, to retrofit features which not available on the host FPGA and prototype novel architectures. In these usecases, achievable clock frequencies of V-FPGA user applications a major concern. The abstraction layer inherently induces overhead, but this aspect is reinforced by nonuniformity effects: When cells perfor...

Unlike ASICs, FPGAs have routing fabrics that are pre-manufactured. And because of this prefabrication, FPGAs hardly can achieve high clock frequencies which offered by ASICs. Thus, there is a need for better FPGA timing performance. And design automation or computer-aided design (CAD) tools for field programmable gate arrays (FPGAs) have played a very critical role over the past decades for FP...

Non-relational database systems (NRDS) such as graph and key-value have gained attention in various trending business analytical application domains. However, while CPU performance scaling becomes increasingly more difficult, field-programmable gate arrays (FPGA)- accelerated NRDS not been systematically studied yet. This survey describes categorizes the inherent differences non-trivial tradeof...

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routin...

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routin...

Although the partially reconfigurable FPGA design is powerful if two different configurations were mapped at compile time to overlapping locations in the FPGA, only one of these configurations can be present in the array at any given moment. They cannot operate simultaneously. However, if somehow the final FPGA location can be determined at runtime, one or both of these overlapping configuratio...

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, b...

Traditional placement algorithms for FPGAs are normally carried out on a fixed clustering solution of a circuit. The impact of clustering on wirelength and delay of the placement solutions is not well quantified. In this paper, we present an algorithm named SCPlace that performs simultaneous clustering and placement to minimize both the total wirelength and longest path delay. We also incorpora...

We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPGA place and route tools to which we can compare. Although the algorithms used are based on previously known approaches, we present several enhancements that improve run-time and quality. We present placement and routin...

FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, congestion, etc) based on geometric distance and/or channel density is no longer accurate for FPGAs. Researchers have shown that the number of segments, instead of geometric (Manhattan) distance, traveled by a net is the ...