Wire routing by optimizing channel assignment within large apertures, " in Proc. Abstract-It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's delay definition is applied. This paper has several objectives. First, it shows that Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. Seco...

Analysis of Elmore delay in distributed RC tree structures shows the influence of both tree cost and tree radius on signal delay in VLSI interconnects. We give new and efficient interconnection tree constructions that smoothly combine the minimum cost and the minimum radius objectives, by combining respectively optimnl algorithms due to Prim and Dijkstra. Previous “shallow-light” techniques [Z]...

CMOS Circuit Veri cation with Symbolic Switch-Level Timing Simulation Clayton B. McDonald ([email protected]) Randal E. Bryant ([email protected]) Electrical and Computer Engineering Department Carnegie Mellon University 5000 Forbes Ave, Pittsburgh, PA 15213 Abstract Symbolic switch-level simulation has been extensively applied to the functional veri cation of CMOS circuitry. We have ex...

In this paper we have put forward an analytical model which can could accurately compute the on chip interconnect delay using distributed RLCG segments. With the increasing level of on chip integration the interconnect delay has acquired prominence for performance driven layout synthesis. Also in higher frequency range of the order of GHz , the effect of shunt conductance and inductance cannot ...

Fast delay estimation methods, as compared to simulation techniques, are needed for incremental performance-driven layout synthesis. On-chip inductive and conductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speeds; circuit complexity and interconnect lengths. Inductance causes noise in the signal waveforms, which can adversely affect the per...

We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-clement (gC) implementations of extended burst-mode asynchronous controllers. Average-case optimization is performed so that frequent paths are accelerated, possibly at the expense of less frequent paths. The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal...

Since 2004, we have been developing an in-situ storage image sensor (ISIS) that captures more than 100 consecutive images at a frame rate of 10 Mfps with ultra-high sensitivity as well as the video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps and above. In order to suppress electro-magnetic noise at such high freq...

We propose to use the dominant time constant of a resistor-capacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, speci cally, semide nite programs (SDPs). For ...

In this brief, we present a simple close-form delay estimate, based on first and second order moments that handle arbitrary voltages and conductance effects for a lumped and distributed line. This proposed model introduces a simple tractable delay formula by incorporating conductance (G) into Resistance, Capacitance (RC) network by preserving the characteristics of the Elmore delay model. The R...

30 b 0 = pl(T new ; b), and q 0 = pl(T new ; v). We now construct ZST T 0 for S by cutting oo the subtree of T rooted at q and replacing it with T new minus the edge between q and z. Since t LD (T 0 ; q) = d(q; s i), it must be that t LD (T 0 ; q) t LD (T; q). If the strict inequality holds, we add extra wire between q and q 0 to enforce equality, and thereby retain zero skew. For convenience, ...