A triple metal double gate (TM-DG) MOSFET with high-k dielectrics has been proposed to overcome the short channel effects. We are using top and bottom metal gates with different work functions to screen the effect of drain (DIBL effect). It has been found that this is effective in reducing the short channel effects. The metal gates have been used to remove the poly silicon depletion of conventi...

We demonstrate Lg = 100 nm high-speed enhancement-mode (E-mode) InAs quantum-well MOSFETs with outstanding high-frequency and logic performance. These devices feature a 3-nm Al2O3 layer grown by atomic layer deposition. The MOSFETs with Lg = 100 nm exhibit VT = 0.2 V (E-mode), RON = 370 Ω · μm, S = 105 mV/dec, DIBL = 100 mV/V, and gm_max = 1720 μS/μm at VDS = 0.5 V. They also have an excellent ...

This paper explains the performance analysis of Gate-AllAround silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length.Gate-All-Aorund (GAA) configuration p...

We optimized a RODOS (reverse-order source/drain formation with double offset spacer) structure in terms of the gate delay (CV/I) and the switching energy (CV). Simulations confirmed that the poly-Si depletion effect, the DC characteristics, the gate delay and the switching energy were enhanced. In the case of 50-nm nMOSFETs, they showed a 794-μA/μm on-current, a 0.1-nA/μm off-current, a 65-mV/...

We report an SRAM with a 90% reduction of activeleakage power achieved by controlling the supply voltage. In our design, the supply voltage of a selected row in the SRAM goes up to 1 V, while that in other memory cells that are not selected is kept at 0.3 V. This suppresses active leakage because of the drain-induced barrier lowering (DIBL) effect. To avoid unexpected flips in the memory cells,...

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangul...

Invention of Transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key to the development of nano electronics technology. This paper offers a brief review of some of the most popular MOSFET structure designs. The scaling down of planar bulk MOSFET proposed by the Moore’s Law has been saturated due to short channel effects a...

The recent development of MOSFET demands innovative approach to maintain the scaling into nanoscale dimension. This paper focuses on the physical nature of vertical MOSFET in nanoscale regime. Vertical structure is one of the promising devices in further scaling, with relaxed-lithography feature in the manufacture. The comparison of vertical and lateral MOSFET performance for nanoscale channel ...

Compact models of short channel effect in symmetric and asymmetric double gate MOSFETs are developed by solving two-dimensional (2-D) Poisson’s equation as a boundary value problem in the subthreshold region. The subthreshold current is obtained through the 2-D analytic potential distribution function. Threshold voltage rolloff, drain induced barrier lowering (DIBL) and subthreshold slope degra...