Electrical through-wafer interconnects (ETWI) are often integrated with inertial sensors for harsh liquid environment applications. Devices with metal interconnects are very susceptible to corrosion in aquatic environments. An alternative approach is to form highly doped, conductive polysilicon through the wafer from the back side (unexposed to harsh environments) to the front side of the devic...

In this paper, we present the experimental results on Critical Dimension (CD) control via real-time temperature control for warped wafers. As opposed to run-to-run control where information from the previous wafer or batch is used for control of the current wafer or batch, the approach here is real-time and make use of current information for control of the current wafer CD. In this paper we de...

Two stacked integration methods have been developed to enable advanced microsystems of microelectromechanical systems (MEMS) on large scale integration (LSI). One is a wafer level transfer of MEMS fabricated on a carrier wafer to a LSI wafer. The other is the use of electrical interconnections using through-Si vias from the structure of a MEMS wafer on a LSI wafer. The wafer level transfer meth...

CD-PEB temperature experiments show that post-exposure bake (PEB) temperature non-uniformity (both in steady-state and transient phases) impacts across-wafer CD uniformity [1]. Continued improvement in CD uniformity requires across-wafer temperature uniformity for the entire PEB cycle. This poses new challenges for the design of PEB thermal modules. This paper proposes a novel PEB thermal modul...

In the past few years, Rapid Thermal Processes (RTP) have gained acceptance as mainstream technology for semi-conductors manufacturing. These processes are characterized by a single wafer processing with a very fast ramp heating of the silicon wafer (up to 200C/sec). The single wafer approach allows for faster wafer processing and better control of process parameters on the wafer. As feature si...

technology with through-silicon vias and low-volume leadfree interconnections K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidt...

Singulation of MEMS is a critical step in the transition from wafer-level to die-level devices. As is the case for capacitive micromachined ultrasound transducer (CMUT) ring arrays, an ideal singulation must protect the fragile membranes from the processing environment while maintaining a ring array geometry. The singulation process presented in this paper involves bonding a trench-patterned CM...

Wafer yield is an important index of efficiency in integrated circuit (IC) production. The number and cluster intensity of wafer defects are two key determinants of wafer yield. As wafer sizes increase, the defect cluster phenomenon becomes more apparent. Cluster indices currently used to describe this phenomenon have major limitations. Causes of process variation can sometimes be identified by...

Process optimization and control in oxide CMP require an understanding of the trade-offs in wafer and die-level uniformity, and their interaction, as functions of the polishing process conditions. We have examined the effects of down force and table speed, the two key factors affecting the polishing rate, on uniformity. Using variation decomposition analysis to decompose the measured variation ...