In Noctuids, storage proteins are taken up into fat body by receptor-mediated endocytosis. These include arylphorin and a second, structurally unrelated very high-density lipoprotein (VHDL). Previously, we have isolated a single storage protein receptor from the corn earworm, Helicoverpa zea, which binds both VHDL and arylphorin. The receptor protein is a basic, N-terminally blocked, approximat...

VHDL and other hardware description languages have become popular as system speci cation languages in top-down design. However, their constructs do not support the behavioral speci cation of embedded systems. We introduce a new conceptual design model, called Program-State Machines, that caters to embedded systems. We then describe the SpecCharts language, an extended version of VHDL, which sup...

We present a rigorous but transparent semantic deenition for VHDL corresponding to the IEEE VHDL'93 standard. Our deenition covers the full behavior of signal and variable assignments as well as the behavior of the various wait statements including delta, time, and postponed cycles. We consider explicitly declared signals, ports, local variables, and shared variables. Our speciication deenes an...

41  Abstract—Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including computers, calculators, video cameras etc. The VHDL (VHSIC Hardware Description Language) has become an essential tool for designers in the world of digital design. This paper presents implementation of a 32-bit Arithmetic Logic Unit (ALU) using VHDL. Here...

This report focuses on models for describing Hardware at di erent re nement levels within High Level Synthesis ow: SFSMD, FSMD and FSM Controlling Datapath. Simple data interfaces are often needed in these models. The hardware description language VHDL is used and tested for implementing these models and interfaces. Problems inherent in the models as well as problems caused by VHDL are discusse...

SMV [McM93] is a language suitable for integrated circuit design and optimized for formal verification. VHDL [IEE93] is a design format suitable for simulation and synthesis, but poorly designed for formal verification purposes. The contribution of this paper is the integration of the two approaches through the definition of systematic rules to translate SMV programs into VHDL descriptions, pro...

The handwritten character recognition system using fuzzy wavelet is modelled using Very High Speed Hardware Description Language (VHDL). The fuzzy wavelet handwritten recognition is a system based on human perception. The time-frequency localization capabilities of wavelet transform in feature extraction enhances the accuracy of recognition at pixel level. The characteristic features of handwri...

In this paper, we define the equivalence of logic circuits and examine their description in VHDL. We can describe logic circuit components as relations between input and output signals in VHDL and implement such circuits on FPGA. In this case, it is necessary to verify the equivalence of VHDL descriptions and the actual logic circuits constructed based on these descriptions. In a previous work,...

This paper proposes a new method to speedup simulation of VHDL models. Therefore, a tool named ATOMS (Automatic Optimization of VHDL Models for Simulation) reads in a VHDL source model and generates automatically a new optimized VHDL model which is simulated faster by the same simulator. ATOMS arises out of an approach to speedup simulation of a RISC computer system running its operating system...