In this paper, a new domino circuit is proposed with low leakage current and high noise immunity which decreases the parasitic capacitance on the dynamic node. This yields a smaller keeper transistors for wide fan-in gates to implement fast and robust circuits. The technique utilized is based on comparison of mirrored current of the pull-up network with its worst case leakage current. Thus, the...

Adder is the paramount circuit for many complex arithmetic operations. The adder cells mainly focus on reduction of power and increasing of speed. For mobile applications, designers work within a limited leakage power specification in order to meet good battery life. The designers apart from leveling of leakage current to ensure correct circuit operation also focuses on minimization of power di...

As the technology is continuously scaled, leakage currents become a major contributor to the total power dissipation. A reduction in power supply voltage is necessary to reduce dynamic power and avoid reliability problems in deep sub-micron (DSM) regimes. Threshold voltage reduction accompanies supply voltage scaling to maintain the performance, but it exponentially increases the subthreshold l...

: In the microprocessors world SRAM play a vital role, but as the technology is scaling in nanometer, leakage current and leakage power both are the most known problems for SRAM cells in low power applications. More than 40% of the total power of the SRAM is waste due to the leakage through transistor. This paper compares the working, performance and results of two different SRAM topologies; a ...

Keywords: Inter-poly dielectric (IPD) ONO Leakage current Bias polarity a b s t r a c t Retention characteristic represents a capability to maintain the storage data and it is related with the reliability of memory device. The retention characteristic is degraded by the leakage of charges from a floating gate to a control gate, and thus the leakage current at low and moderate electric field of ...

Abstract: An ultra-low power (ULP), power gated static random access memory (SRAM) is presented for Internet of Things (IoT) applications, which operates in sub-threshold voltage ranges from 300mV to 500mV. The proposed SRAM has tendency to operate in low supply voltages with high static and dynamic noise margins. The IoT application involves battery enabled low leakage memory architecture in s...

In modern high performance integrated circuits, maximum of the total active mode energy is consumed due to leakage current. SRAM cell array is main source of leakage current since majority of transistor are utilized for on-chip memory in today high performance microprocessor and system on chip designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply volt...

A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using power gating reduction technique is presented. The circuit achieves the large driving capability by employing simple comparators to sense the transients of the input to turn on the output stages, which are statically off in the stable state. The effect of the different number of transistor...

From the last few decades, the scaling down of CMOS devices have been taking place to achieve better performance in terms of speed, power dissipation, size and reliability. The major area of concern in today‟s CMOS technology is Data retention and leakage current reduction. SRAM (Static Random Access Memory) is memory used to store data. Conventional Static Random Access Memory (SRAM) cells suf...

There is a growing body of literature that points to the significant potential of carbon capture and sequestration technologies to help society address the challenge posed by climate change. In particular, carbon capture and sequestration appears to be a fundamental key to controlling the costs of addressing climate change. Within this literature, there is also speculation that the retention of...