In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed des...

The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power...

In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simul...

This paper presents 1-bit full adder cell in emerging technologies like FinFET and CNFET that operates in the moderate inversion region for energy efficiency, robustness and higher performance. The performance of the adder is improved by the optimum selection of important process parameters like oxide and fin thickness in FinFET and number of carbon nanotubes, chirality vector and pitch in CNFE...

In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay pr...

Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4to 20-bits are considered for the less significant adder bit positions. The simulation results show that approx...

   This paper presents a novel design of quaternary logic gates using graphene nanoribbon field effect transistors (GNRFETs). GNRFETs are the alternative devices for digital circuit design due to their superior carrier-transport properties and potential for large-scale processing. In addition, Multiple-valued logic (MVL) is a promising alternative to the conventional binary logic design. Sa...

-In current scenario, VLSI circuit’s greatest challenges is to reduce the power dissipation and surface area so that longer life and high performance achieved to greater extent. The key parameter is threshold voltage to reduce the leakage power. In our proposal, we design low power and high performance JK flip-flop. JK flip-flop is designed with the help of D flip-flop and with some logic gates...

Full adders are essentially used as a building block in all arithmetic, DSP and microprocessor applications. In this paper, a 15 transistor hybrid PTL-TG full adder circuit is proposed. The main objective is to provide high speed, low power, full swing operation with good drivability. The choice of logic design affects the circuit performance. The delay time depends on the number of transistors...

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Transient (SET) immunity. This novel can tolerate particles as charge injection in different internal nodes, well the input output nodes. The of new circuit has been assessed through key parameters, such power consumption, delay, Power-Delay Product (PDP) at various fr...