Incorporation of deuterium to passivate silicon-dangling bonds at the Si-SiO2 interface through ion implantation before the growth of the gate oxide is the focus of this work. Polycrystalline silicon gate n-channel metal-oxide-semiconductor diodes with 4 nm gate oxide grown on deuterium-implanted p-type silicon ^100& substrate were investigated. Deuterium implanted at a light dose of 1 3 10/cm ...

The main interface and interconnection materials normally used in complementary metal-oxide semiconductor (CMOS) integrated circuit processing, i.e. silicon oxides and aluminum, were evaluated with regards to deoxyribonucleic acid (DNA) attachment. We investigated and quantified the influence of various techniques of fabrication of the silicon oxide on DNA binding obtained by four different bio...

In this paper, a novel device architecture called the fully depleted silicon-on-insulator field-effect transistor with block oxide (bFDSOI-FET) is proposed to investigate the influence of block oxide height (HBO) on the electrical characteristics. According to the two-dimensional (2-D) simulation results, the characteristics of the proposed structure are similar to those of the ultra-thin (UT) ...

The electrical properties of polymeric thin film transisitors (P-TFTs) based on poly(9,9-dioctylfluorene-cobithiophene) alternating copolymer (F8T2) have been studied. Device performance was compared for amorphous silicon nitride deposited by LPCVD and PECVD techniques, aluminum oxide deposited by sputtering, titanium oxide deposited by sputtering, and thermal silicon oxide gate dielectrics. A ...

Ultrathin silicon-on-insulator, composed of a crystalline sheet of silicon bounded by native oxide and a buried oxide layer, is extremely resistive because of charge trapping at the interfaces between the sheet of silicon and the oxide. After chemical modification of the top surface with hydrofluoric acid (HF), the sheet resistance drops to values below what is expected based on bulk doping alo...

The solid-phase crystallization of an amorphous silicon film to polycrystalline silicon by a low-temperature ~<600 °C! furnace anneal has been investigated in a suspended cantilever structure without underlying silicon oxide by transmission electron microscopy and Raman spectroscopy. The grain size of polysilicon increases up to ;3.0 mm and the density of intragranular defects decreases one ord...

Scaling the gate oxide thickness is one of many process development challenges facing device engineers today. Nitrogen implantation has been used to control gate oxide thickness. By varying the dose of the nitrogen implant, process engineers can have multiple gate oxide thicknesses in the same process. Although it has been observed that nitrogen retards gate oxidation kinetics, the physics of h...

Semiconductor flash memory is an indispensable component of modern electronic systems. The minimum feature size of an individual CMOSFET has shrunk to 15nm with an equivalent gate oxide thickness (EOT) of 0.8nm in 2001. However, semiconductor flash memory scaling is far behind CMOS logic device scaling. For example, the EOT of the gate stack in semiconductor flash memory is still more than 10nm...

A nitride spacer with an underlying deposited tetraethoxysilane oxide, that behaves as a convenient etch stop layer, is a popular choice for sidewall spacer in modern complementary metal–oxide– semiconductor process flows. In this work we have investigated the effect of the silicon nitride spacer process on the boron profile in silicon and the related dose loss of B from the Si into the silicon...

In the organic field effect transistors (OFETs) generation, the silicon gate oxide is 1-2 nm thick. A shrinking of this thickness down to less than 1 nm for the next generation will led to a couple of orders of magnitude increase in tunnelling as well as leakage currents. NiO-SiO2 can be used in a variety of devices, such as in circuit boards and detectors, including sensors, due to its porous ...