With these issues in mind, we designed an audio-controlled digital oscillograph that uses an audio recognition algorithm to control the oscillograph; specifically, it controls the waveform display size attenuation and amplification as well as the scanning speed. The oscillograph display uses a standard VGA interface that can display waveforms on a PC monitor, projector, or other standard output...

We present a Hardware/software (HW/SW) implementation of an artificial neural network aims at detecting whether or not that the targeted X ray images of breast contain cancerous cell. This system has been trained in order to approximate functions or to achieve classification from a limited number of data. We implemented our application on FPGA by using the soft processor NIOS II.

The purpose of this study is to develop a motion sensor (delivering optical flow estimations) using a platform that includes the sensor itself, focal plane processing resources, and co-processing resources on a general purpose embedded processor. All this is implemented on a single device as a SoC (System-on-a-Chip). Optical flow is the 2-D projection into the camera plane of the 3-D motion inf...

[1] The modification of near‐surface near‐inertial oscillations (NIOs) by the geostrophic vorticity is studied globally from an observational standpoint. Surface drifter are used to estimate NIO characteristics. Despite its spatial resolution limits, altimetry is used to estimate the geostrophic vorticity. Three characteristics of NIOs are considered: the relative frequency shift with respect t...

An Advanced Standard Encryption Algorithm (AES) is widely used in modern consumer electronic products for security. The IEEE 802.15.4 Low-Rate wireless sensor networks also use AES algorithm where low power consumption is the priority. To reduce the time taken for encryption of huge data, the algorithm has to be implemented in hardware. To meet the requirement for low area the algorithm has to ...

Navigation and obstacle avoidance are some of the important tasks or mission deployed and accomplished by an autonomous mobile robot. This paper presents the designed obstacle avoidance program for mobile robot that incorporates a neuro-fuzzy algorithm using Altera Field Programmable Gate Array (FPGA) development board. To generate collisionfree path for mobile robot, a proper motion planning i...

This paper describes scalable Montgomery Multiplication (MM) coprocessor optimized for Altera NIOS embedded processor implemented in reconfigurable hardware. Features of the NIOS soft processor Avalon Bus are used to connect the coprocessor as a memory mapped peripheral so that the overall performance is improved. Implemented coprocessor performs modular MM with large numbers (up to 4096 bits),...