Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are invalidated by hazards caused primarily due to non-zero delays of off-path circuit elements. Thus, non-robust tests are of limited value when process variations change gate delays. We propose a bounded gate delay model for test quality evaluat...

This brief addresses the problem of implementing very large constant multiplications by a single variable under shift-adds architecture using minimum number adders/subtractors. Due to intrinsic complexity problem, we introduce an approximate algorithm, called TÕLL, which partitions constants into smaller ones. To reduce operations, TÕLL incorporates graph-based and common subexpression eliminat...

In Chapter 6 we learned that oblivious unitand multi-delay simulation may require several gate simulations to be performed for a single gate. These extra gate-simulations significantly increase simulation time over oblivious zero-delay simulation. The Parallel Technique was introduced as a method of speeding up these additional gate simulations. Chapter 2 introduced the concept of bit-parallel ...

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the circuitdelay variation, so it is important to characterize each gate-delay variation accurately. Every transistor in a gate affects transient characteristics of the gate, so it is indispensable to consider an intrag...

Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such that the delay of a combinational circuit is minimized while the cost constraint is satisfied. It is one of the most studied problems in VLSI computer-aided design. Despite this, all of the existing techniques are heuri...

Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (f(T)) of graphene transistor generally increases with the reduced gate length (L(gate)) till L(gate) = 40 nm, and the maximum measured f(T) has reached 300 GHz. Using ab initio quantum transport simulation, we reveal fo...

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay (VID) g...

The choice of gate metal technology for junctionless transistors needs to have diverse characteristics as metals distinct work functions and hence, they show incompatibility while tailoring threshold the device. In such a scenario, bimetallic stacked can be promising candidate present wide range tunable required nano-regime transistors. This paper explores electronic phenomena occurring at meta...

Gate resizing for minimum circuit delay is a fundamental problem in the performance optimization of gate-level circuits. In this paper , we study the complexity of two diierent minimum-delay gate resizing problems for combinational circuits composed of single-output gates. The rst problem is that of gate resizing for minimum circuit delay under the load-dependent delay model. The second problem...