The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at source-channel region is proposed and modeled this paper. gate oxide TFET stacked configuration high-k over low-k to improve control without any lattice mismatches. Tangent Line Approximation (TLA) method used here model accurately. validated by...

Interest in the integration of graphene and semiconductor nanowires (NWs) increased dramatically during last two decades along with overwhelming development technology. The possibility combining countless properties singular optical behavior NWs leads way to design unique photonic nanodevices. In this work, response Si/SiGe axially heterostructured deposited over a monolayer is investigated. re...

In this study, we analyzed the total ionizing dose (TID) effect characteristics of p-type FinFET and Nanowire FET (NW-FET) according to structural aspect through comparison two devices. Similar n-type devices, NW-FETs are less affected than FinFETs by TID effect. For inverter circuit simulation, both n- p-types NW-FET were regarding The operation considering was verified using Berkeley short-ch...

Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken deal with for field effect transistor further scale down as semiconductor technology enters into sub-10 nm node. From 3 node beyond, gate all around steps onto the history stage attributed its improved SCE suppressing ability thanks surrounding s...

A novel gate-all-around (GAA) poly-Si nanowire (NW) floating gate (FG) memory device was fabricated and characterized. The enhanced electric field around the corners of the nanowire channels boosts the P/E process and thus the operation voltages are dramatically lowered. Furthermore, the non-localized trapping feature characteristic of the FG makes the injection or ejection of electrons easier ...

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nmthin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-n...

The interface trap charges (ITC) associated reliability analysis of a charge-plasma based asymmetric double-gate (ADG) dopingless tunnel field effect transistor (DLTFET) with Si/Ge heterojunction and high-κ gate dielectric (HJADGDLTFET) has been studied. HJADGDLTFET uses silicon at the drain channel region, germanium source which enhances band-to-band tunnelling source-channel junction, hence d...