FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important iss...

Placement of functional units on an FPGA fabric is a challenging problem for runtime reconfigurable computing systems. We introduce the concept of physical contexts to greatly reduce the complexity of the placement and routing problems. We have implemented static and dynamic linear placement methods for expression trees placed in physical contexts. Our placement algorithms are implemented in th...

In this paper, we present an optimized design flow to map Register-Transfer-Level (RTL) netlists onto multiple-FPGA architectures. Our FPGA-dedicated method fully exploits design structure by letting the basic design steps technology mapping, hierarchical partitioning, floorplanning and signal flow driven placement, interact. This efficiently reduces runtime and yields design implementations of...

This paper presents an analytical model that relates the architectural parameters of an FPGA to the place-and-route runtimes of the FPGA CAD tools. We consider both a simulated annealing based placement algorithm employing a bounding-box wirelength cost function, and a negotiationbased A* router. We also show an example application of the model in early architecture evaluation.

The increasing size of modern field programmable gate arrays (FPGAs) allows for ever more complex applications to be mapped onto them. However, long design implementation times large designs can severely affect productivity. A modular methodology improve productivity in a divide and conqueror fashion but at the expense degraded performance power consumption resulting implementation. To reduce d...

In this paper we present a self con gurable multiplication technique allowing vari able con guration time for a class of LUT based Field Programmable Gate Arrays FPGAs which exist today We show this technique to be implementable on FPGA architectures allowing internally addressable RAM primitives to be directly mapped to the Logic Elements LEs of the logic resource This provides run time read w...

Although the new generations of FPGAs provide support for partial and dynamic configuration, the huge reconfiguration latency is still a major shortcoming of the current FCCMs . Software and hardware techniques (compiler optimizations, configuration prefetching) have been used in order to reduce the impact of the configuration overhead on the overall performance. Nevertheless, these techniques ...

Harnessing human computation is an approach to find problem solutions. In this paper, we investigate harnessing this human computation for a Field Programmable Gate Array (FPGA) placement problem. We create a game called Plummings. In this game, a player attempts to reduce the critical path of a digital design mapped to an FPGA by swapping clusters on the array, but the problem details are abst...

As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be developed. Before designing low-power FPGA circuitry, architectures, or CAD tools, we must first determine where the biggest savings (in terms of energy dissipation) are to be made and whether these savings are cumulative. I...