The readout of detector arrays requires the monolithic or hybrid integration of a integrate circuit multiplexer with the detector array. In most LWIR and VLWIR applications, a hybrid approach is used. For example, the detector array may be built from HgCdTe and the readout integrated circuit may be silicon CMOS [1]. The two integrated circuits are mated through a bump-bonding process in which e...

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less tha...

There have recently been more and more reports on CMOS integrated circuits operating at terahertz (≥ 0.1THz) frequencies. However, design environments and techniques are not as well established as for RF CMOS circuits. This paper reviews recent progress made by the authors in terahertz CMOS design for low-power and high-speed wireless communication, including device characterization and modelin...

As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltages well under 1 V. Although dramatic power reductions can be achieved using low supply voltages in high performance applications, the increased subthreshold leakage that results when transistor threshold voltages are l...

The imbalanced utilization and the diversity of circuitry cause on-chip temperature gradients. Different sections of high-performance integrated circuits typically operate at different temperatures. Furthermore, environmental temperature fluctuations can cause significant variations in the die temperature. Temperature fluctuations alter the speed characteristics of CMOS circuits. Several techni...

Today, complex systems are mainly integrated in CMOS technology, which is facing issues in advanced process nodes, in particular for power consumption and heat dissipation. Magnetic devices such as Magnetic Tunnel Junction (MTJ) have specific features: non-volatility, high cyclability (more than 10) and immunity to radiations. Combined with CMOS devices they offer specific and new features to d...

Local long-term adaptation is a well-known feature of the synaptic junctions in nerve tissue. Neuroscientists have demonstrated that biology uses local adaptation both to tune the performance of neural circuits and for long-term learning. Many researchers believe it is key to the intelligent behavior and the efficiency of biological organizms. Although engineers use adaptation in feedback circu...

Presented method of on-line detection of overloads and short circuits in digital devices and systems is based on inexpensive overload detectors built into integrated circuits. A prototype 0.8 μm CMOS ASIC successfully verifies this method.

CMOS faces new device and technology challenges: MOSFETs require ultra-sharp doping profiles and complex processing; integration of devices into circuits requires arbitrary interconnection with overlay precision beyond known manufacturing solutions (3σ=±3nm, 16nm CMOS, ITRS’11[1]). To overcome these challenges, we propose a new nanoscale computing fabric with integrated design of device, interc...