The goal of this work was to model the influence of the substrate skin effects on the distributed mutual impedance per unit length parameters of multiple coupled onchip interconnects. The proposed analytic model is based on the frequency-dependent distribution of the current in the silicon substrate and the closed form integration approach. It is shown that the calculated frequency-dependent di...

This paper presents an in-depth investigation into the avalanche breakdown robustness of commercial state-of-the-art silicon carbide (SiC) power MOSFETs comprising of functional as well as structural characterization and the corresponding underlying physical mechanisms responsible for device failure. One aspect of robustness for power MOSFETs is determined by its ability to withstand energy dur...

MOS Technology on massive substrate played a critical task during micro-electronic evolution. The regular reduction of transistors sizes leads today to nanometric devices. With this reduction, some parasitic physical effects, previously with no importance, became mostly amplified, leading to the end of MOSFETs technology on massive substrate. SOI technology gives a good alternative to that mini...

A 3-D simulation of single event effects (SEEs) for domestic Silicon–Germanium heterojunction bipolar transistor (SiGe HBT) in extreme environment is performed with TCAD simulation tools. The influences of environment temperature and linear energy transfer (LET) on SEE are investigated. The combined effects of temperature and LET are also discussed. The results show some interesting phenomena b...

Silicon-based CMOS technologies are predicted to reach their ultimate limits by the middle of the next decade. Research on nanotechnologies is actively conducted in a world-wide effort to develop new technologies able to maintain the Moore’s law. They promise revolutionizing the computing systems by integrating tremendous numbers of devices at low cost. These trends will provide new computing o...

SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing but requires more sophisticated device and circuit design to reduce the effects of the floating-body. FD-SOI device design potentially has the advantage of no floating-body effects but requires very thin silicon films making manufacturing more chall...

Future nano scale devices will expose different characteristics than todays silicon devices. While the exponential growth of non recurring expenses (NRE, mostly due to mask sets) can be anticipated even for new technologies, problems such as the dramatically increased defect density require new approaches to build functional devices at reasonable prices. Improved CAD algorithms can help to solv...

The growing gap between processor and memory speeds makes memory issues a major bottleneck in the design of systems-on-silicon. When the system is designed for a targeted application (as is the case with embedded systems-onsilicon), several strategies can be employed to resolve this memory bandwidth bottleneck, including reorganization of data, exploiting locality of reference to tune the memor...

Passive components for use in planar Monolithic Microwave Integrated Circuits (MMICs) based on High Electron Mobility Transistors (HEMTs) on indium phosphide substrates are presented. Design, fabrication, and modeling issues of capacitors, resistors, inductors, transmission lines, via holes, and air bridges have been addressed. Sputtered thin films have been utilized to make metal-insulator-met...

Atomic force microscope (AFM) based local anodic oxidation of metallic and semiconducting layers has emerged as a powerful tool for nanoscale fabrication. A unique nanoscale patterning technique has been created that couples computer aided design (CAD) with the lithographic capabilities of the AFM. Target nanostructures to be deposited on a silicon substrate are rendered as a three-dimensional ...