In this paper, a formal design approach for the differential cascode voltage switch with pass gate (DCVSPG) logic is presented. This permits the design of any combinational logic function by the use of a k-map or by a modified QuineMcCluskey algorithm. The basic design approach used is based on pass logic and shows that a DCVSPG logic gate designed with minimum number of transistors may not alw...

This open-loop gain enhancement circuit in 1.2pm CMOS does not require cascode or long-channel transistors, thus maximizing output swing and input common-mode range [1,21. Since gain enhancement is achieved not by increasing output resistance, but by matching main and replica amplifiers, high effective open-loop gain is maintained even with resistive loads. This circuit can be used with any tra...

The effect of gate – drain/source underlap ( Lun ) on a narrow band LNA performance has been studied , in 30 nm FinFET using device and mixed mode simulations. Studies are done by maintaining and not maintaining the leakage current (Ioff) of the various devices. LNA circuit with two transistors in a cascode arrangement is constructed and the input impedance, gain and noise-figure have been used...

A novel low voltage self-biased high swing cascode current mirror (SHCCM) employing bulk-driven NMOS transistors is proposed in this paper. The comparison with the conventional circuit reveals that the proposed bulk-driven circuit operates at lower voltages and provides enhanced bandwidth with improved output resistance. The proposed circuit is further modified by replacing the passive resistan...

Three circuit techniques are proposed that provide (with simultaneous use) an increase bymore than two orders of magnitude the maximum output voltage slew rate (SR) microelectronicoperational amplifiers (op-amps) based on bipolar transistors with a classical architecture,designed to operate in automatic control systems, radio engineering and communications, forexample, as drivers for ultra-high...

This paper presents the design and analysis of a 5.5 V Class-D stage used in two fully integrated watt-level, +32.0 dBm and +29.7 dBm, outphasing RF Power Amplifiers (PA) in standard 130 nm and 65 nm CMOS technologies. The Class-D stage utilizes a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V technologies without excessive device vol...

A current mirror (CM) based on self cascode MOSFETs low voltage analog and mixed mode structures has been proposed. The proposed CM has high output impedance and can operate at 0.5 V. P-Spice simulations confirm the high performance of this CM with a bandwidth of 6.0 GHz at input current of 100 μA. Keywords—Current Mirrors, Composite Cascode Structure, Current Source/Sink.

Source-drain follower has been designed and implemented for monolithically integrated biosensor array. The circuit acts as a voltage follower, in which a sensing transistor is operated at fixed gatesource and gate-drain voltages. It operates at 10 nW power dissipation. The wide-swing cascode configurations are investigated in constant and non-constant biasing methods. The constant biased cascod...