نتایج جستجو برای: retention leakage noise low

تعداد نتایج: 1442580  

2012
Pascal Andreas Meinerzhagen Oskar Andersson Babak Mohammadi S. M. Yasser Sherazi Andreas Peter Burg Joachim Neves Rodrigues

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-VT) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforward approach to realize robust subVT storage arrays and fill the gap of missing sub-VT memory compilers. This paper presents an ultra-low-leaka...

Journal: :Microelectronics Journal 2005
Huifang Qin Yu Cao Dejan Markovic Andrei Vladimirescu Jan M. Rabaey

Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the data retention voltage (DRV), leakage power can be substantially reduced. This paper models the DRV of a standard low leakage SRAM module as a function of process and design parameters, and analyzes the SRAM cell stability when VDD approaches DRV. ...

2013
Nahid Rahman B. P. Singh

Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As modern technology is spreading fast, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very muc...

2016
Sonam Jain

Low power SRAM memory designs has become challenging for portable device applications. Semiconductor/ VLSI industry growth has exponentially demanding low leakage power SRAM designs for high performance chips and microprocessors. To get optimized standard cell memory design for battery operated devices at deep sub micron CMOS technology, a low leakage Asynchronous 8T SRAM is proposed. In this p...

In this paper, a new circuit scheme is proposed to reduce the power consumption of dynamic circuits. In the proposed circuit, an NMOS keeper transistor is used to maintain the voltage level in the output node against charge sharing, leakage current and noise sources. Using the proposed keeper scheme, the voltage swing on the dynamic node is lowered to reduce the power consumption of wide fan-in...

2009
A. Bouloukou

This paper presents the design, fabrication and characterisation of InGaAs–InAlAs high electron mobility transistors (pHEMTs) suitable for low-frequency LNA designs. Very low levels of leakage, in the order of 0.05A/cm, are demonstrated by the pHEMTs, which have enabled the implementation of large-geometry, low-noise devices. Transistors with gate widths ranging from 200mm to 1.2mm are demonstr...

2008

A low-noise, 2.5V reference is constructed by stacking four 2.5V reference ICs in series. The resulting 10V output is divided back to 2.5V, and a low-noise unity-gain buffer added. This stacked-reference design reduces noise because the noise from each IC, being random and uncorrelated, partially cancels each other out. The low-frequency 1/f noise (LF noise) generated by a voltage reference at ...

2017
P. RAIkwAL V. NEEMA A. VERMA

Memory has been facing several problems in which the leakage current is the most severe. Many techniques have been proposed to withstand leakage control such as power gating and ground gating. In this paper a new 8T SRAM cell, which adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high hold static noise margin. The proposed cell with low threshol...

Journal: :J. Low Power Electronics 2006
Huifang Qin Rakesh Vattikonda Thuan Trinh Yu Cao Jan M. Rabaey

This paper proposes a comprehensive SRAM cell optimization scheme that minimizes leakage power under ultra-low standby supply voltage (VDD). The theoretical limit of data retention voltage (DRV), the minimum VDD that preserves the states of a memory cell, was derived to be 50 mV for an industrial 90 nm technology. A DRV design model was developed on parameters including body bias, sizing, and c...

Journal: :Quantum Information & Computation 2007
Panos Aliferis Barbara M. Terhal

We provide a rigorous analysis of fault-tolerant quantum computation in the presence of local leakage faults. We show that one can systematically deal with leakage by using appropriate leakage-reduction units such as quantum teleportation. The leakage noise is described by a Hamiltonian and the noise is treated coherently, similar to general non-Markovian noise analyzed in Refs. [TB05] and [AGP...

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