Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance co...

In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces the Hydra: a network interface for the MONTIUM TP, a coarse-grained reconfigurable processor desig...

Optical Network-on-Chip (ONoC) is a promising emerging technology, which can solve the bottlenecks faced by electrical on-chip interconnection. However, the existing proposals of ONoC are mostly built on fixed topologies, which are not flexible enough to support various applications. To make full use of the limited resource and provide a more efficient approach for resource allocation, RONoC (R...

With the increasing complexity of Multi-Core System-on-Chip (MCSoC) and its communications requirement, Network-on-Chip (NoC) has emerged as a solution of nonscalable shared bus schemes currently used in MCSoC implementation. Recently, a new NoC structure based on WKrecursive network was analyzed and compared to 2D Mesh structure based on several performance metrics such as packet losses, throu...

Networks on Chip (NoC) has emerged as the paradigm for designing scalable communication architecture for Systems on Chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. The deadlocks th...

Modern chip-scale computing system performance is increasingly becoming determined by the characteristics of the interconnection network. Photonic technology has been proposed as an alternative to traditional electronic interconnects for its advantages in bandwidth density, latency, and power efficiency. Circuit-switched photonic network architectures take advantage of the optical spectrum to c...

The input buffers of the current packet-switched Network-on-Chip (NoC) architectures consume a significant portion of the total power of the interconnection network. Reducing the size of input buffers would result in degraded performance, while eliminating all buffers would result in increased power at high network load. In this article, we propose DXbar: an innovative dual-crossbar design. By ...

A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication infrastructure, components placed at run-time on a device can mutually communicate. A 4x4 dynamic network-on-chip communication infrastructure prototype, implemented in an FPGA occupies only 7% of the device area and c...

With the rise of many-core chips that require substantial bandwidth from the network on chip (NoC), integrated photonic links have been investigated as a promising alternative to traditional electrical interconnects. While numerous optoelectronic NoCs have been proposed, evaluations of photonic architectures have thus-far had to use a number of simplifications, reflecting the need for a modelin...