2014 X-ray transmission topographies made during thermal cycles from the paraelectric phase to the lock-in transition temperature on [N(CD3)4]2ZnCl4 crystals of very good crystalline quality have shown (i) a precipitation of defects near the lock-in transition and (ii) pseudo-periodic contrasts which disappear in the paraelectric phase. J. Physique LETTRES 44 (1983) L-963-L-970 ler DÉCEMBRE 198...

In this paper a new architecture for delay locked loops will be presented.  One of problems in phase-frequency detectors (PFD) is static phase offset or reset path delay. The proposed structure decreases the jitter resulted from PFD by switching two PFDs. In this new architecture, a conventional PFD is used before locking of DLL to decrease the amount of phase difference between input and outpu...

We implement a simple computer-based photon-counting lock-in that combines the signal-to-noise benefits of photon counting with lock-in detection. We experimentally specify the flatness and the noise characteristics of a flexible software implementation. The noise of amplitude and phase of the small signal is at the limit of photonic shot noise; from 1000 counted photons we reach an amplitude r...

In previous work, we have shown that second-order phase locked loop (PLL) with sinusoidal phase detector characteristics have a separatrix cycle for a certain value of closed loop gain. It was verified that bifurcation from a stable separatrix cycle is the mechanism responsible for breaking the limit cycle associated with the PLL’s out-of lock state and the loop pulls in (phase lock). The value...

The Brookhaven National Laboratory Relativistic Heavy Ion Collider (RHIC) has two beam synchronous event links (BSL), one for each ring, which use the 28 MHz ring low level rf to distribute event codes synchronously with a precise phase relationship to the beam. During a cogging reset just before injection, the low level rf sine wave is interrupted which causes the BSL receivers to lose lock. L...

Abstract |We consider carrier phase and symbol timing synchronization for M-ary partial-response continuous phase modulation (CPM).We focus on developing a classical phase locked loop (PLL)-basedmethod that is robust even forM-ary partial-response CPMs, which has proven to be elusive thus far in the literature. A key part of our design is a simple yet ešective timing false lock detector, which ...

The high performance of today's digital phase-lock loop makes it the preferred choice for generation of stablee low noisee tunable local oscillators in wireless communications applicationss This paper investigates the design of passive loop filters for Frequency Synthesizers utilizing a Phase-Frequency Detector and a current switch charge pump such as National Semiconductor's PLLatinum TM Serie...