Abstract This work presents a novel approach to water Cherenkov neutrino detector event reconstruction and classification. Three forms of Convolutional Neural Network have been trained reject cosmic muon events, classify beam estimate energies, using only slightly modified version the raw as input. When evaluated on realistic selection simulated CHIPS-5kton prototype this new significantly incr...

The nematode Caenorhabditis elegans is a widely adopted model organism for studying various neurobiological processes at the molecular and cellular level in vivo. With a small, flexible, and continuously moving body, the manipulation of C. elegans becomes a challenging task. In this review, we highlight recent advances in microfluidic technologies for the manipulation of C. elegans. These new f...

The design of a new high-performance computing platform to model biological neural networks requires scalable, layered communications in both hardware and software. SpiNNaker’s hardware is based upon Multi-Processor System-on-Chips (MPSoCs) with flexible, power-efficient, custom communication between processors and chips. The architecture scales from a single 18-processor chip to over 1 million...

This paper presents SIRENA, a CAD environment for the simulation and modeling of mixed-signal VLSI parallel processing chips based on Cellular Neural Networks. SIRENA includes capabilities for: a) the description of nominal and non-ideal operation of CNN analog circuitry at the behavioral level; b) performing realistic simulations of the transient evolution of physical CNNs including deviations...

Ki-Chul Kim Dept. of Info and Comm KAIST Seoul, 130-012, Korea This paper describes a way of neural hardware implementation with the analog-digital mixed mode neural chip. The full custom neural VLSI of Universally Reconstructible Artificial Neural network (URAN) is used to implement Korean speech recognition system. A multi-layer perceptron with linear neurons is trained successfully under the...

This paper presents a digital architecture with on-chip learning for Hoppeld attractor neural networks with binary weights. A new learning rule for the binary weights network is proposed that allows pattern storage up to capacity = 0:4 and incurs very low hardware overhead. Due to the use of binary couplings the network has minimal storage requirements. A exible communication structure allows t...

This paper presents SIRENA, a CAD environment for the simulation and modeling of mixed-signal VLSI parallel processing chips based on Cellular Neural Networks. SIRENA includes capabilities for: a) the description of nominal and non-ideal operation of CNN analog circuitry at the behavioral level; b) performing realistic simulations of the transient evolution of physical CNNs including deviations...

This paper suggests the systolic array implementation of block based Hopfield neural network architecture using completely digital circuits. The design is based on rewriting the energy equation of Hopfield neural network to a systolic (or modular) form. The performance of the proposed architecture is evaluated by applying various binary inputs and it is observed that the network provides massiv...