Parsing a Spice netlist is the first step of all circuit simulation programs. This part is usually done by low-level coding techniques in C or Fortran language. The aim of this paper is to show the usefulness of functional programming techniques to the needs of scientific computing. Key-Words: Spice Netlist, Parsing, Scanning, Functional Language.

A logic style known as Phased Logic(PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timed implementation. Bit level dataflow, early evaluation and automatic filtering of transient computations within PL circuits can lead to both increased performance and higher energy efficiency than the origi...

AbstructThis paper presents effective algorithms for multiway partitioning. Confirming ideas originally due to Hall, we demonstrate that geometric embeddings of the circuit netlist can lead to high-quality k-way partitionings. The netlist embeddings are derived via the computation of d eigenvectors of the Laplacian for a graph representation of the netlist. As Hall did not specify how to partit...

A power plant simulation tool (‘PowerSim’) has been developed with 10 years experience from the development of a plant simulator for efficient modeling of a power plant. PowerSim is the first developed tool in Korea for plant simulation with various plant component models, instructor station function and the Graphic Model Builder (GMB). PowerSim is composed of a graphic editor using general pur...

Delay minimization and power minimization are two important objectives in the design of the high-performance, portable, and wireless computing and communication systems. Retiming is a very effective way for delay optimization for sequential circuits. In this paper we propose a unified framework for multi-level partitioning and floorplanning with retiming, targeting simultaneous delay and power ...

The spectral method can lead to a high quality of multi-way partition due to its ability to capture global netlist information. For spectral partition, n netlist modules are mapped to n points in d-dimensional space, and then a linear ordering of these n modules is constructed to be used as a basis for partitioning. In this paper, we propose two clustering based linear ordering algorithms takin...

Components An abstract component α is a triple (I, O,S), where I and O are sets of input and output signals, respectively, and S is a formal specification defining allowed input-output behavior of the component. An instance of an abstract component α is any circuit or netlist that satisfies the specification S of α. We illustrate the notion of an abstract component using an example. Example 2. ...

Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate betw...

Timing Aware Partitioning for Multi-FPGA Based Logic Simulation Using Top-down Selective Flattening. (August 2012) Subramanian Poothamkurissi Swaminathan, B.Tech., National Institute of Technology, Trichy, India Chair of Advisory Committee: Dr. Sunil P. Khatri In order to accelerate logic simulation, it is highly beneficial to simulate the circuit design on FPGA hardware. However, limited hardw...

this paper mainly focused on implementation of aes encryption and decryption standard aes-128. all the transformations of both encryption and decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. this method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theaes inversesub bytes module and...