This paper discusses the type of capacitances for Single Gate MOSFET and Double Gate MOSFET including their quantity. The effect of parasitic capacitance makes double gate MOSFET more suitable component for the designing of digital logic switches than single gate MOSFET. Here, we introducing Independent double gate MOSFET operation based on VeSFET concept. Then introducing with the total capaci...

In this article, a novel concept is introduced to improve the radio frequency (RF) linearity of partially-depleted (PD) silicon-on-insulator (SOI) MOSFET circuits. The transition due to the non-zero body resistance (RBody) in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free c...

According to Moore’s law, the number of transistor embedded on integrated circuit (IC) doubles approximately every two years. Thus, the size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has to be scaled down as an increase in packing density. In current technology, the size of a transistor has shrunk below 45nm, and it has already reached its physical limit. Any attempt to shri...

This article presents some design guidelines for the RCD snubber of flyback converters. When the MOSFET turns off, a high-voltage spike occurs on the drain pin because of a resonance between the leakage inductor (Llk) of the main transformer and the output capacitor (COSS) of the MOSFET. The excessive voltage on the drain pin may lead to an avalanche breakdown and eventually damage the MOSFET. ...

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well...

This article presents some design guidelines for the RCD snubber of flyback converters. When the MOSFET turns off, a high-voltage spike occurs on the drain pin because of a resonance between the leakage inductor (Llk) of the main transformer and the output capacitor (COSS) of the MOSFET. The excessive voltage on the drain pin may lead to an avalanche breakdown and eventually damage the MOSFET. ...

Low-power, compact, and highperformance NP dynamic CMOS circuits are presented in this paper assuming a 16 nm carbon nano tube transistor technology. The performances of two-stage pipeline 32-bit carry lookahead adders are evaluated based on HSPICE simulation with the following four different implementations: silicon MOSFET (Si-MOSFET) domino logic, Si-MOSFET NP dynamic CMOS, carbon nanotube MO...

| We present formula of propagation delay for static CMOS logic gates considering short-circuit current and current owing through gate capacitance and using the n-th power law MOSFET model which considers velocity saturation e ects. The short circuit current is represented by a piece-wise linear function, which enables detailed analysis of the transient behavior of a CMOS inverter. We found tha...

-The first part of this article presents the modeling of the long-channel bulk MOSFET as a particular case of the SOI MOSFET. The second part reviews compares and scrutinizes various methods to extract the threshold voltage, the effective channel and the individual values of drain and source resistances. These are important device parameters for modeling and circuit simulation.