In this paper we address the complexity issues associated with gate duplication for delay optimization. Gate duplication for general circuits has been proved NP-Complete [1]. In this paper we show that even the local delay optimization by gate duplication is NPComplete. Local fanout optimization (bu er insertion) for xed net topology can be solved in polynomial time [9]. Even the global fanout ...

On The Complexity Of Gate Duplication Ankur Srivastava, Ryan Kastner and Majid Sarrafzadeh Computer Science Department, University of California Los Angeles Abstract|In this paper we show that both the global and local gate duplication problems for delay optimization are NP-complete under certain delay models. Keywords|Gate Duplication, required time, satis ability, VLSI, NP-Completeness.

A macromodeling and timing simulation technique is presented that allows fast, accurate delay calculations for CMOS circuits. This method is well suited for delay calculations of regular structure VLSI circuits, as well as circuits designed from standard cell libraries. Timing models for both logic gate and transmission gate circuit forms are developed. For logic gates, output transition time a...

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ̄ ariable input dela...

Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive numbe...

The worst-case carry propagation delays in carryskip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. We report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do ...

Optimizing gate scheduling at airports is an old, but also a broad problem. The main purpose of this problem is to find an assignment for the flights arriving at and departing from an airport, while satisfying a set of constraints.A closer look at the literature in this research line shows thatin almost all studies airport gate processing time has been considered as a fix parameter. In this res...

In most libraries, gate parameters such as the pin-to-pin intrinsic delays, load-dependent coefficients, and input pin capacitances have different values for rising and falling signals. Most performance optimization algorithms, however, assume a single value for each parameter. It is known that under the load-independent delay model, the gate assignment (or resizing) problem is solvable in time...