This paper presents a novel algorithm and architecture for digital frequency synthesis DFS . It is based on a simple difference equation. Simulation results show that the proposed DFS algorithm is preferable to the conventional phase-locked-loop frequency synthesizer and the direct digital frequency synthesizer in terms of the spurious-free dynamic range SFDR and the peak-signalto-noise ratio P...

This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 m CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistag...

This paper presents a fully integrated multi-band frequency-synthesizer architecture. The synthesizer is a ∆Σ based fractional-N frequency synthesizer with three on-chip LC tuned VCOs to cover the entire frequency bands specified in IEEE802.11b, and 802.11a WLAN standards. The synthesizer includes a ∆Σ noise shaper, a dead-zone-free phase frequency detector and a fully differential charge pump....

This paper reviews several techniques used to reduce the in-band phase noise contribution of fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of 97 dBc/Hz@10 KHz for an RF output frequency of 2.432...

This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthe...

In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the perform...

In this paper, a new pure-digital frequency synthesizer Fout=(X/Y)•Fin for square-waves with controlled precision is described. Given that Fin is the input reference frequency provided by a stable crystal oscillator, Fout is the synthesized frequency; X and Y are two co-prime integer numbers. The purpose is to demonstrate that with exclusively simple digital techniques, a frequency synthesizer ...

A fully integrated dual-mode frequency synthesizer for GSM and Wideband CDMA (WCDMA) is presented. The synthesizer is designed to maximize hardware sharing between the two modes by applying fractional frequency synthesis to GSM mode and integer frequency synthesis to WCDMA mode. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divide...

This paper presents a low power CMOS frequency synthesizer for GPS application that can support multiple reference clocks. The frequency synthesizer has fractional-N phase locked loop structure with sigma-delta modulator to allow multiple reference clock frequencies. The measured phase noise is -126dBc/Hz at 1MHz offset from the carrier. This chip is fabricated with 0.18 m CMOS technology, and ...