We report a 72.8 GHz fully static frequency divider in AIInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than OdBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8GHz. Power dissipation per flip-flop is 55mW with a 3.1V power supply. To our knowledge this is the highest frequency of o...

A 1 V low voltage delta-sigma fractional-N frequency divider for multi-band (780/868/915 MHz and 2.4 GHz) WSN frequency synthesizers is presented. The frequency divider consists of a dual-modulus prescaler, a pulse-swallow counter and a delta-sigma modulator. The high-speed and low-voltage phase-switching dualmodulus prescaler is used in the frequency divider. Low threshold voltage transistors ...

A high-speed triple-modulus frequency divider (FD) is designed and fabricated in a 90-nm CMOS process. With three pairs of nMOS switches inserted in the signal paths of the regenerative divider, the FD can offer three selectable division ratios of 1/2, 1/3, and 1/4. The corresponding behavior model of the proposed divider is utilized to explain the operation principle and analyze the locking ra...

In this paper, dual-frequency O-shaped 3-way Bagley power divider is designed and analysed. Equal split power division is achieved at arbitrary design Frequencies. In this structure, two-section transmission line transformer is used to realize the dual-frequency operation. This paper describes a new Bagley power divider on a single-layer micro strip line that can reduce the occupied area. To va...

Abstract—This paper presents a novel tri-band unequal Wilkinson power divider. The proposed structure is derived from the conventional unequal Wilkinson power divider by replacing the quarter-wavelength branch lines and quarter-wavelength transformers with the extended T-shaped short stubs and three-section transformers respectively. The first and third operating frequencies of the proposed Wil...

An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

Superharmonic injection locking is investigated in a new theoretical approach. Low power frequency dividers are designed using injection locked oscillators with cascode transistors. The Rockwell 0:5 m CMOS process is used to design a 3mW injection locked frequency divider in the 1800MHz frequency range. A 200MHz maximum locking range is achieved in simulations. 2SC3302 TOSHIBA NPN transistors a...

In this paper, PLL are most frequently used for Local Oscillator (LO) signal generation in wireless radio transceivers to down convert the carrier frequency to lower or intermediate frequency . The input reference frequency is 6.4 MHz. The architecture used for the design of Frequency synthesizer was Integer-N architecture. This was designed using 0.25 μm technology. The VCO designed was a CMOS...

This paper first presents the architecture of a frequency synthesizer which can support multistandard wireless systems of GPS, Galileo, and WCDMA standards. Then, a programmable integer/fractional combined frequency divider (CFD), which is the key building block of the proposed frequency synthesizer, is designed and implemented by using 0.18μm RF CMOS process. The CFD mainly consists of an inte...

|A voltage controlled di erential injection locked frequency divider (VCDILFD) with a large locking range is designed in a 0:24 m CMOS technology. A 29% locking range is achieved by an optimal inductor design and also by employing high Q accumulation mode MOS varactors to change the free{running oscillation frequency of the divider. The measurement results show frequency division at 5GHz with m...