A further research on floorplanning considering multi clock domains is presented in this paper, which concentrates on interconnection between different clock domains. This contributes to simplification of clock tree and signal routing between different clock domains. Experimental results show that better floorplan can be obtained through our floorplanning proposed in this paper. Key-Words: Floo...

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will...

Floorplanning is an essential step in physical design of VLSI. The floorplan design problem is how to place a set of circuit modules on a chip such that the resulting area is minimized. The best known solutions are obtained using simulated annealing based on sequence pairs representing the planning of modules. The conventional simulated annealing algorithm conducts a random perturbation operati...

Floorplanning plays a vital role in the physical design process of Very Large Scale Integrated (VLSI) chips. It is an essential design step to estimate the chip area prior to the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, many optimization techniques were adopted in the literature. In this work, a music-inspired Harmony Sear...

Floorplanning is an essential step in VLSI chip design automation. The main objective of the floorplanning is to find a floorplan such that the cost is minimized. This is achieved by minimizing the chip area and interconnection cost. It determines the performance, size, yield and reliability of VLSI chips. We propose a Memetic Algorithm (MA) for non-slicing and hard module VLSI floorplanning pr...

This chapter is focused on the physical design for system-on-a-chip (SOC). Physical design refers to all synthesis steps that convert a circuit representation (gates, transistors) into a geometric representation (polygons and theirs shapes). See Figure 1 for an illustration. The geometric representation, also called layout , is used to design masks and then manufacture a chip. As a very complic...

Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan layout. Although CL has proven to have the same search space and time complexity as Corne...